fifo_buffer.v

一个深度为32

`timescale 1ns/1ns
module FIFO_Buffer(
Data_out,                         //FIFO out data pipe
stack_full,                       //status symbol
stack_half_full,
stack_empty,
Data_in,                          //FIFO in data pipe
write_to_stack,                   //write control sig
read_from_stack,                  //read control sig
clk,rst
);
parameter stack_width = 8 ;       //width of data&stack
parameter stack_height = 32 ;     //height of stack
parameter stack_ptr_width = 5 ;   //stack point width
parameter HF_level = 16 ;         //stack half full
output [stack_width - 1:0]        Data_out;
output                            stack_full,stack_half_full,stack_empty;
input  [stack_width - 1:0]        Data_in;
input                             write_to_stack,read_from_stack;
input                             clk,rst;

reg    [stack_ptr_width - 1:0]    read_ptr,write_ptr; //address
reg    [stack_ptr_width:0]        ptr_gap;
reg    [stack_width - 1:0]        Data_out;
reg    [stack_width - 1:0]        stack[stack_height - 1:0];//establish a stack

//stack signal
assign stack_full = (ptr_gap == stack_height); //full signal
assign stack_half_full = (ptr_gap == HF_level);//half full signal
assign stack_empty = (ptr_gap == 0);           //empty signal

always@(posedge clk or posedge rst)
 if(rst)begin
  Data_out <= 0;
  read_ptr <= 0;
  
  write_ptr <= 0;
  ptr_gap <= 0;
 end
 else if (write_to_stack && (!stack_full) && (!read_from_stack))begin
  stack[write_ptr] <= Data_in;
  write_ptr <= write_ptr + 1;
  ptr_gap <= ptr_gap + 1;
 end
 else if (read_from_stack && (!stack_empty) && (!write_to_stack))begin
  Data_out <= stack[read_ptr];
  read_ptr <= read_ptr + 1;
  ptr_gap <= ptr_gap - 1;
 end
 else if (write_to_stack && read_from_stack && stack_empty)begin
  stack[write_ptr] <= Data_in;
  write_ptr <= write_ptr + 1;
  ptr_gap <= ptr_gap + 1;
 end
  else if (write_to_stack && read_from_stack && stack_full)begin
  Data_out <= stack[read_ptr];
  read_ptr = read_ptr + 1;
  ptr_gap <= ptr_gap - 1;
 end
 else if (write_to_stack && read_from_stack && (!stack_empty) && (!stack_full))begin
  Data_out <= stack[read_ptr];
   stack[write_ptr] <= Data_in;
   read_ptr <= read_ptr + 1;
   write_ptr <= write_ptr + 1;
 end
endmodule