t_fifo_buffer.v

一个深度为32

`timescale 1ns/1ns
module t_FIFO_Buffer ();
 parameter              stack_width = 8;
 parameter              stack_height = 32;
 parameter              stack_ptr_width = 6;
 
 wire   [stack_width - 1:0]      Data_out;
 wire                            write;
 wire                            stack_full,stack_half_full,stack_empty;
 reg    [stack_width - 1:0]      Data_in;
 reg                             write_to_stack,read_from_stack;
 reg                             clk,rst;
 wire   [stack_width - 1:0]      stack0,stack1,stack2,stack3,stack4,stack5,
                                 stack6,stack7,stack8,stack9,stack10,stack11,
                                 stack12,stack13,stack14,stack15,stack16,stack17,
                                 stack18,stack19,stack20,stack21,stack22,stack23,
                                 stack24,stack25,stack26,stack27,stack28,stack29,
                                 stack30,stack31;
                                  
 assign stack0 = M1.stack[0];
 assign stack1 = M1.stack[1];
 assign stack2 = M1.stack[2];
 assign stack3 = M1.stack[3];
 assign stack4 = M1.stack[4];
 assign stack5 = M1.stack[5];
 assign stack6 = M1.stack[6];
 assign stack7 = M1.stack[7];
 assign stack8 = M1.stack[8];
 assign stack9 = M1.stack[9];
 assign stack10 = M1.stack[10];
 assign stack11 = M1.stack[11];
 assign stack12 = M1.stack[12];
 assign stack13 = M1.stack[13];
 assign stack14 = M1.stack[14];
 assign stack15 = M1.stack[15];
 assign stack16 = M1.stack[16];
 assign stack17 = M1.stack[17];
 assign stack18 = M1.stack[18];
 assign stack19 = M1.stack[19];
 assign stack20 = M1.stack[20];
 assign stack21 = M1.stack[21];
 assign stack22 = M1.stack[22];
 assign stack23 = M1.stack[23];
 assign stack24 = M1.stack[24];
 assign stack25 = M1.stack[25];
 assign stack26 = M1.stack[26];
 assign stack27 = M1.stack[27];
 assign stack28 = M1.stack[28];
 assign stack29 = M1.stack[29];
 assign stack30 = M1.stack[30];
 assign stack31 = M1.stack[31];
 
 FIFO_Buffer M1 (Data_out,stack_full,stack_half_full,stack_empty,
                 Data_in,write_to_stack,read_from_stack,clk,rst);

initial #300 $finish;
initial begin rst = 1;#2 rst = 0;end
initial begin clk = 0;forever #4 clk = ~clk; end

initial begin Data_in = 8'hFA;
 @(posedge write_to_stack);
  repeat (24)@(negedge clk) Data_in = ~ Data_in;
end

//write to FIFO
initial fork
 begin #8 write_to_stack = 0; end
 begin #16 write_to_stack = 1;#140 write_to_stack = 0;end
 begin #224 write_to_stack = 1; end
join

//read from FIFO
initial fork
 begin #8 read_from_stack = 0; end
 begin #64 read_from_stack = 1;#40 read_from_stack = 0; end
 begin #144 read_from_stack = 1;#8 read_from_stack = 0; end
 begin #176 read_from_stack = 1;#56 read_from_stack = 0; end
join
endmodule