📄 msp430x14x.h
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#define CAPD7 (0x80) /* Comp. A Disable Input Buffer of Port Register .7 */
/************************************************************
* ADC12
************************************************************/
#define ADC12CTL0_ (0x01A0) /* ADC12 Control 0 */
DEFW( ADC12CTL0 , ADC12CTL0_)
#define ADC12CTL1_ (0x01A2) /* ADC12 Control 1 */
DEFW( ADC12CTL1 , ADC12CTL1_)
#define ADC12IFG_ (0x01A4) /* ADC12 Interrupt Flag */
DEFW( ADC12IFG , ADC12IFG_)
#define ADC12IE_ (0x01A6) /* ADC12 Interrupt Enable */
DEFW( ADC12IE , ADC12IE_)
#define ADC12IV_ (0x01A8) /* ADC12 Interrupt Vector Word */
DEFW( ADC12IV , ADC12IV_)
#define ADC12MEM_ (0x0140) /* ADC12 Conversion Memory */
#ifndef __IAR_SYSTEMS_ICC
#define ADC12MEM (ADC12MEM_) /* ADC12 Conversion Memory (for assembler) */
#else
#define ADC12MEM ((int*) ADC12MEM_) /* ADC12 Conversion Memory (for C) */
#endif
#define ADC12MEM0_ (0x0140) /* ADC12 Conversion Memory 0 */
DEFW( ADC12MEM0 , ADC12MEM0_)
#define ADC12MEM1_ (0x0142) /* ADC12 Conversion Memory 1 */
DEFW( ADC12MEM1 , ADC12MEM1_)
#define ADC12MEM2_ (0x0144) /* ADC12 Conversion Memory 2 */
DEFW( ADC12MEM2 , ADC12MEM2_)
#define ADC12MEM3_ (0x0146) /* ADC12 Conversion Memory 3 */
DEFW( ADC12MEM3 , ADC12MEM3_)
#define ADC12MEM4_ (0x0148) /* ADC12 Conversion Memory 4 */
DEFW( ADC12MEM4 , ADC12MEM4_)
#define ADC12MEM5_ (0x014A) /* ADC12 Conversion Memory 5 */
DEFW( ADC12MEM5 , ADC12MEM5_)
#define ADC12MEM6_ (0x014C) /* ADC12 Conversion Memory 6 */
DEFW( ADC12MEM6 , ADC12MEM6_)
#define ADC12MEM7_ (0x014E) /* ADC12 Conversion Memory 7 */
DEFW( ADC12MEM7 , ADC12MEM7_)
#define ADC12MEM8_ (0x0150) /* ADC12 Conversion Memory 8 */
DEFW( ADC12MEM8 , ADC12MEM8_)
#define ADC12MEM9_ (0x0152) /* ADC12 Conversion Memory 9 */
DEFW( ADC12MEM9 , ADC12MEM9_)
#define ADC12MEM10_ (0x0154) /* ADC12 Conversion Memory 10 */
DEFW( ADC12MEM10 , ADC12MEM10_)
#define ADC12MEM11_ (0x0156) /* ADC12 Conversion Memory 11 */
DEFW( ADC12MEM11 , ADC12MEM11_)
#define ADC12MEM12_ (0x0158) /* ADC12 Conversion Memory 12 */
DEFW( ADC12MEM12 , ADC12MEM12_)
#define ADC12MEM13_ (0x015A) /* ADC12 Conversion Memory 13 */
DEFW( ADC12MEM13 , ADC12MEM13_)
#define ADC12MEM14_ (0x015C) /* ADC12 Conversion Memory 14 */
DEFW( ADC12MEM14 , ADC12MEM14_)
#define ADC12MEM15_ (0x015E) /* ADC12 Conversion Memory 15 */
DEFW( ADC12MEM15 , ADC12MEM15_)
#define ADC12MCTL_ (0x0080) /* ADC12 Memory Control */
#ifndef __IAR_SYSTEMS_ICC
#define ADC12MCTL (ADC12MCTL_) /* ADC12 Memory Control (for assembler) */
#else
#define ADC12MCTL ((char*) ADC12MCTL_) /* ADC12 Memory Control (for C) */
#endif
#define ADC12MCTL0_ (0x0080) /* ADC12 Memory Control 0 */
DEFC( ADC12MCTL0 , ADC12MCTL0_)
#define ADC12MCTL1_ (0x0081) /* ADC12 Memory Control 1 */
DEFC( ADC12MCTL1 , ADC12MCTL1_)
#define ADC12MCTL2_ (0x0082) /* ADC12 Memory Control 2 */
DEFC( ADC12MCTL2 , ADC12MCTL2_)
#define ADC12MCTL3_ (0x0083) /* ADC12 Memory Control 3 */
DEFC( ADC12MCTL3 , ADC12MCTL3_)
#define ADC12MCTL4_ (0x0084) /* ADC12 Memory Control 4 */
DEFC( ADC12MCTL4 , ADC12MCTL4_)
#define ADC12MCTL5_ (0x0085) /* ADC12 Memory Control 5 */
DEFC( ADC12MCTL5 , ADC12MCTL5_)
#define ADC12MCTL6_ (0x0086) /* ADC12 Memory Control 6 */
DEFC( ADC12MCTL6 , ADC12MCTL6_)
#define ADC12MCTL7_ (0x0087) /* ADC12 Memory Control 7 */
DEFC( ADC12MCTL7 , ADC12MCTL7_)
#define ADC12MCTL8_ (0x0088) /* ADC12 Memory Control 8 */
DEFC( ADC12MCTL8 , ADC12MCTL8_)
#define ADC12MCTL9_ (0x0089) /* ADC12 Memory Control 9 */
DEFC( ADC12MCTL9 , ADC12MCTL9_)
#define ADC12MCTL10_ (0x008A) /* ADC12 Memory Control 10 */
DEFC( ADC12MCTL10 , ADC12MCTL10_)
#define ADC12MCTL11_ (0x008B) /* ADC12 Memory Control 11 */
DEFC( ADC12MCTL11 , ADC12MCTL11_)
#define ADC12MCTL12_ (0x008C) /* ADC12 Memory Control 12 */
DEFC( ADC12MCTL12 , ADC12MCTL12_)
#define ADC12MCTL13_ (0x008D) /* ADC12 Memory Control 13 */
DEFC( ADC12MCTL13 , ADC12MCTL13_)
#define ADC12MCTL14_ (0x008E) /* ADC12 Memory Control 14 */
DEFC( ADC12MCTL14 , ADC12MCTL14_)
#define ADC12MCTL15_ (0x008F) /* ADC12 Memory Control 15 */
DEFC( ADC12MCTL15 , ADC12MCTL15_)
/* ADC12CTL0 */
#define ADC12SC (0x001) /* ADC12 Start Conversion */
#define ENC (0x002) /* ADC12 Enable Conversion */
#define ADC12TOVIE (0x004) /* ADC12 Timer Overflow interrupt enable */
#define ADC12OVIE (0x008) /* ADC12 Overflow interrupt enable */
#define ADC12ON (0x010) /* ADC12 On/enable */
#define REFON (0x020) /* ADC12 Reference on */
#define REF2_5V (0x040) /* ADC12 Ref 0:1.5V / 1:2.5V */
#define MSC (0x080) /* ADC12 Multiple SampleConversion */
#define SHT00 (0x0100) /* ADC12 Sample Hold 0 Select 0 */
#define SHT01 (0x0200) /* ADC12 Sample Hold 0 Select 1 */
#define SHT02 (0x0400) /* ADC12 Sample Hold 0 Select 2 */
#define SHT03 (0x0800) /* ADC12 Sample Hold 0 Select 3 */
#define SHT10 (0x1000) /* ADC12 Sample Hold 0 Select 0 */
#define SHT11 (0x2000) /* ADC12 Sample Hold 1 Select 1 */
#define SHT12 (0x4000) /* ADC12 Sample Hold 2 Select 2 */
#define SHT13 (0x8000) /* ADC12 Sample Hold 3 Select 3 */
#define MSH (0x080)
#define SHT0_0 (0*0x100u)
#define SHT0_1 (1*0x100u)
#define SHT0_2 (2*0x100u)
#define SHT0_3 (3*0x100u)
#define SHT0_4 (4*0x100u)
#define SHT0_5 (5*0x100u)
#define SHT0_6 (6*0x100u)
#define SHT0_7 (7*0x100u)
#define SHT0_8 (8*0x100u)
#define SHT0_9 (9*0x100u)
#define SHT0_10 (10*0x100u)
#define SHT0_11 (11*0x100u)
#define SHT0_12 (12*0x100u)
#define SHT0_13 (13*0x100u)
#define SHT0_14 (14*0x100u)
#define SHT0_15 (15*0x100u)
#define SHT1_0 (0*0x1000u)
#define SHT1_1 (1*0x1000u)
#define SHT1_2 (2*0x1000u)
#define SHT1_3 (3*0x1000u)
#define SHT1_4 (4*0x1000u)
#define SHT1_5 (5*0x1000u)
#define SHT1_6 (6*0x1000u)
#define SHT1_7 (7*0x1000u)
#define SHT1_8 (8*0x1000u)
#define SHT1_9 (9*0x1000u)
#define SHT1_10 (10*0x1000u)
#define SHT1_11 (11*0x1000u)
#define SHT1_12 (12*0x1000u)
#define SHT1_13 (13*0x1000u)
#define SHT1_14 (14*0x1000u)
#define SHT1_15 (15*0x1000u)
/* ADC12CTL1 */
#define ADC12BUSY (0x0001) /* ADC12 Busy */
#define CONSEQ0 (0x0002) /* ADC12 Conversion Sequence Select 0 */
#define CONSEQ1 (0x0004) /* ADC12 Conversion Sequence Select 1 */
#define ADC10SSEL0 (0x0008) /* ADC12 Clock Source Select 0 */
#define ADC10SSEL1 (0x0010) /* ADC12 Clock Source Select 1 */
#define ADC10DIV0 (0x0020) /* ADC12 Clock Divider Select 0 */
#define ADC10DIV1 (0x0040) /* ADC12 Clock Divider Select 1 */
#define ADC10DIV2 (0x0080) /* ADC12 Clock Divider Select 2 */
#define ISSH (0x0100) /* ADC12 Invert Sample Hold Signal */
#define SHP (0x0200) /* ADC12 Sample/Hold Pulse Mode */
#define SHS0 (0x0400) /* ADC12 Sample/Hold Source 0 */
#define SHS1 (0x0800) /* ADC12 Sample/Hold Source 1 */
#define CSTARTADD0 (0x1000) /* ADC12 Conversion Start Address 0 */
#define CSTARTADD1 (0x2000) /* ADC12 Conversion Start Address 1 */
#define CSTARTADD2 (0x4000) /* ADC12 Conversion Start Address 2 */
#define CSTARTADD3 (0x8000) /* ADC12 Conversion Start Address 3 */
#define CONSEQ_0 (0*2u)
#define CONSEQ_1 (1*2u)
#define CONSEQ_2 (2*2u)
#define CONSEQ_3 (3*2u)
#define ADC12SSEL_0 (0*8u)
#define ADC12SSEL_1 (1*8u)
#define ADC12SSEL_2 (2*8u)
#define ADC12SSEL_3 (3*8u)
#define ADC12DIV_0 (0*0x20u)
#define ADC12DIV_1 (1*0x20u)
#define ADC12DIV_2 (2*0x20u)
#define ADC12DIV_3 (3*0x20u)
#define ADC12DIV_4 (4*0x20u)
#define ADC12DIV_5 (5*0x20u)
#define ADC12DIV_6 (6*0x20u)
#define ADC12DIV_7 (7*0x20u)
#define SHS_0 (0*0x400u)
#define SHS_1 (1*0x400u)
#define SHS_2 (2*0x400u)
#define SHS_3 (3*0x400u)
#define CSTARTADD_0 (0*0x1000u)
#define CSTARTADD_1 (1*0x1000u)
#define CSTARTADD_2 (2*0x1000u)
#define CSTARTADD_3 (3*0x1000u)
#define CSTARTADD_4 (4*0x1000u)
#define CSTARTADD_5 (5*0x1000u)
#define CSTARTADD_6 (6*0x1000u)
#define CSTARTADD_7 (7*0x1000u)
#define CSTARTADD_8 (8*0x1000u)
#define CSTARTADD_9 (9*0x1000u)
#define CSTARTADD_10 (10*0x1000u)
#define CSTARTADD_11 (11*0x1000u)
#define CSTARTADD_12 (12*0x1000u)
#define CSTARTADD_13 (13*0x1000u)
#define CSTARTADD_14 (14*0x1000u)
#define CSTARTADD_15 (15*0x1000u)
/* ADC12MCTLx */
#define INCH_0 (0)
#define INCH_1 (1)
#define INCH_2 (2)
#define INCH_3 (3)
#define INCH_4 (4)
#define INCH_5 (5)
#define INCH_6 (6)
#define INCH_7 (7)
#define INCH_8 (8)
#define INCH_9 (9)
#define INCH_10 (10)
#define INCH_11 (11)
#define INCH_12 (12)
#define INCH_13 (13)
#define INCH_14 (14)
#define INCH_15 (15)
#define SREF_0 (0*0x10u)
#define SREF_1 (1*0x10u)
#define SREF_2 (2*0x10u)
#define SREF_3 (3*0x10u)
#define SREF_4 (4*0x10u)
#define SREF_5 (5*0x10u)
#define SREF_6 (6*0x10u)
#define SREF_7 (7*0x10u)
#define EOS (0x80)
/************************************************************
* Interrupt Vectors (offset from 0xFFE0)
************************************************************/
#define PORT2_VECTOR (1 * 2u) /* 0xFFE2 Port 2 */
#define USART1TX_VECTOR (2 * 2u) /* 0xFFE4 USART 1 Transmit */
#define USART1RX_VECTOR (3 * 2u) /* 0xFFE6 USART 1 Receive */
#define PORT1_VECTOR (4 * 2u) /* 0xFFE8 Port 1 */
#define TIMERA1_VECTOR (5 * 2u) /* 0xFFEA Timer A CC1-2, TA */
#define TIMERA0_VECTOR (6 * 2u) /* 0xFFEC Timer A CC0 */
#define ADC_VECTOR (7 * 2u) /* 0xFFEE ADC */
#define USART0TX_VECTOR (8 * 2u) /* 0xFFF0 USART 0 Transmit */
#define USART0RX_VECTOR (9 * 2u) /* 0xFFF2 USART 0 Receive */
#define WDT_VECTOR (10 * 2u) /* 0xFFF4 Watchdog Timer */
#define COMPARATORA_VECTOR (11 * 2u) /* 0xFFF6 Comparator A */
#define TIMERB1_VECTOR (12 * 2u) /* 0xFFF8 Timer B CC1-6, TB */
#define TIMERB0_VECTOR (13 * 2u) /* 0xFFFA Timer B CC0 */
#define NMI_VECTOR (14 * 2u) /* 0xFFFC Non-maskable */
#define RESET_VECTOR (15 * 2u) /* 0xFFFE Reset [Highest Priority] */
#define UART1TX_VECTOR USART1TX_VECTOR
#define UART1RX_VECTOR USART1RX_VECTOR
#define UART0TX_VECTOR USART0TX_VECTOR
#define UART0RX_VECTOR USART0RX_VECTOR
/************************************************************
* End of Modules
************************************************************/
#pragma language=default
#endif /* #ifndef __msp430x14x */
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