📄 msp430x14x.h
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#define P2IN_ (0x0028) /* Port 2 Input */
READ_ONLY DEFC( P2IN , P2IN_)
#define P2OUT_ (0x0029) /* Port 2 Output */
DEFC( P2OUT , P2OUT_)
#define P2DIR_ (0x002A) /* Port 2 Direction */
DEFC( P2DIR , P2DIR_)
#define P2IFG_ (0x002B) /* Port 2 Interrupt Flag */
DEFC( P2IFG , P2IFG_)
#define P2IES_ (0x002C) /* Port 2 Interrupt Edge Select */
DEFC( P2IES , P2IES_)
#define P2IE_ (0x002D) /* Port 2 Interrupt Enable */
DEFC( P2IE , P2IE_)
#define P2SEL_ (0x002E) /* Port 2 Selection */
DEFC( P2SEL , P2SEL_)
/************************************************************
* DIGITAL I/O Port3/4
************************************************************/
#define P3IN_ (0x0018) /* Port 3 Input */
READ_ONLY DEFC( P3IN , P3IN_)
#define P3OUT_ (0x0019) /* Port 3 Output */
DEFC( P3OUT , P3OUT_)
#define P3DIR_ (0x001A) /* Port 3 Direction */
DEFC( P3DIR , P3DIR_)
#define P3SEL_ (0x001B) /* Port 3 Selection */
DEFC( P3SEL , P3SEL_)
#define P4IN_ (0x001C) /* Port 4 Input */
READ_ONLY DEFC( P4IN , P4IN_)
#define P4OUT_ (0x001D) /* Port 4 Output */
DEFC( P4OUT , P4OUT_)
#define P4DIR_ (0x001E) /* Port 4 Direction */
DEFC( P4DIR , P4DIR_)
#define P4SEL_ (0x001F) /* Port 4 Selection */
DEFC( P4SEL , P4SEL_)
/************************************************************
* DIGITAL I/O Port5/6
************************************************************/
#define P5IN_ (0x0030) /* Port 5 Input */
READ_ONLY DEFC( P5IN , P5IN_)
#define P5OUT_ (0x0031) /* Port 5 Output */
DEFC( P5OUT , P5OUT_)
#define P5DIR_ (0x0032) /* Port 5 Direction */
DEFC( P5DIR , P5DIR_)
#define P5SEL_ (0x0033) /* Port 5 Selection */
DEFC( P5SEL , P5SEL_)
#define P6IN_ (0x0034) /* Port 6 Input */
READ_ONLY DEFC( P6IN , P6IN_)
#define P6OUT_ (0x0035) /* Port 6 Output */
DEFC( P6OUT , P6OUT_)
#define P6DIR_ (0x0036) /* Port 6 Direction */
DEFC( P6DIR , P6DIR_)
#define P6SEL_ (0x0037) /* Port 6 Selection */
DEFC( P6SEL , P6SEL_)
/************************************************************
* USART
************************************************************/
/* UxCTL */
#define PENA (0x80) /* Parity enable */
#define PEV (0x40) /* Parity 0:odd / 1:even */
#define SPB (0x20) /* Stop Bits 0:one / 1: two */
#define CHAR (0x10) /* Data 0:7-bits / 1:8-bits */
#define LISTEN (0x08) /* Listen mode */
#define SYNC (0x04) /* UART / SPI mode */
#define MM (0x02) /* Master Mode off/on */
#define SWRST (0x01) /* USART Software Reset */
/* UxTCTL */
#define CKPH (0x80) /* SPI: Clock Phase */
#define CKPL (0x40) /* Clock Polarity */
#define SSEL1 (0x20) /* Clock Source Select 1 */
#define SSEL0 (0x10) /* Clock Source Select 0 */
#define URXSE (0x08) /* Receive Start edge select */
#define TXWAKE (0x04) /* TX Wake up mode */
#define STC (0x02) /* SPI: STC enable 0:on / 1:off */
#define TXEPT (0x01) /* TX Buffer empty */
/* UxRCTL */
#define FE (0x80) /* Frame Error */
#define PE (0x40) /* Parity Error */
#define OE (0x20) /* Overrun Error */
#define BRK (0x10) /* Break detected */
#define URXEIE (0x08) /* RX Error interrupt enable */
#define URXWIE (0x04) /* RX Wake up interrupt enable */
#define RXWAKE (0x02) /* RX Wake up detect */
#define RXERR (0x01) /* RX Error Error */
/************************************************************
* USART 0
************************************************************/
#define U0CTL_ (0x0070) /* USART 0 Control */
DEFC( U0CTL , U0CTL_)
#define U0TCTL_ (0x0071) /* USART 0 Transmit Control */
DEFC( U0TCTL , U0TCTL_)
#define U0RCTL_ (0x0072) /* USART 0 Receive Control */
DEFC( U0RCTL , U0RCTL_)
#define U0MCTL_ (0x0073) /* USART 0 Modulation Control */
DEFC( U0MCTL , U0MCTL_)
#define U0BR0_ (0x0074) /* USART 0 Baud Rate 0 */
DEFC( U0BR0 , U0BR0_)
#define U0BR1_ (0x0075) /* USART 0 Baud Rate 1 */
DEFC( U0BR1 , U0BR1_)
#define U0RXBUF_ (0x0076) /* USART 0 Receive Buffer */
READ_ONLY DEFC( U0RXBUF , U0RXBUF_)
#define U0TXBUF_ (0x0077) /* USART 0 Transmit Buffer */
DEFC( U0TXBUF , U0TXBUF_)
/* Alternate register names */
#define UCTL0 U0CTL /* USART 0 Control */
#define UTCTL0 U0TCTL /* USART 0 Transmit Control */
#define URCTL0 U0RCTL /* USART 0 Receive Control */
#define UMCTL0 U0MCTL /* USART 0 Modulation Control */
#define UBR00 U0BR0 /* USART 0 Baud Rate 0 */
#define UBR10 U0BR1 /* USART 0 Baud Rate 1 */
#define RXBUF0 U0RXBUF /* USART 0 Receive Buffer */
#define TXBUF0 U0TXBUF /* USART 0 Transmit Buffer */
#define UCTL0_ U0CTL_ /* USART 0 Control */
#define UTCTL0_ U0TCTL_ /* USART 0 Transmit Control */
#define URCTL0_ U0RCTL_ /* USART 0 Receive Control */
#define UMCTL0_ U0MCTL_ /* USART 0 Modulation Control */
#define UBR00_ U0BR0_ /* USART 0 Baud Rate 0 */
#define UBR10_ U0BR1_ /* USART 0 Baud Rate 1 */
#define RXBUF0_ U0RXBUF_ /* USART 0 Receive Buffer */
#define TXBUF0_ U0TXBUF_ /* USART 0 Transmit Buffer */
#define UCTL_0 U0CTL /* USART 0 Control */
#define UTCTL_0 U0TCTL /* USART 0 Transmit Control */
#define URCTL_0 U0RCTL /* USART 0 Receive Control */
#define UMCTL_0 U0MCTL /* USART 0 Modulation Control */
#define UBR0_0 U0BR0 /* USART 0 Baud Rate 0 */
#define UBR1_0 U0BR1 /* USART 0 Baud Rate 1 */
#define RXBUF_0 U0RXBUF /* USART 0 Receive Buffer */
#define TXBUF_0 U0TXBUF /* USART 0 Transmit Buffer */
#define UCTL_0_ U0CTL_ /* USART 0 Control */
#define UTCTL_0_ U0TCTL_ /* USART 0 Transmit Control */
#define URCTL_0_ U0RCTL_ /* USART 0 Receive Control */
#define UMCTL_0_ U0MCTL_ /* USART 0 Modulation Control */
#define UBR0_0_ U0BR0_ /* USART 0 Baud Rate 0 */
#define UBR1_0_ U0BR1_ /* USART 0 Baud Rate 1 */
#define RXBUF_0_ U0RXBUF_ /* USART 0 Receive Buffer */
#define TXBUF_0_ U0TXBUF_ /* USART 0 Transmit Buffer */
/************************************************************
* USART 1
************************************************************/
#define U1CTL_ (0x0078) /* USART 1 Control */
DEFC( U1CTL , U1CTL_)
#define U1TCTL_ (0x0079) /* USART 1 Transmit Control */
DEFC( U1TCTL , U1TCTL_)
#define U1RCTL_ (0x007A) /* USART 1 Receive Control */
DEFC( U1RCTL , U1RCTL_)
#define U1MCTL_ (0x007B) /* USART 1 Modulation Control */
DEFC( U1MCTL , U1MCTL_)
#define U1BR0_ (0x007C) /* USART 1 Baud Rate 0 */
DEFC( U1BR0 , U1BR0_)
#define U1BR1_ (0x007D) /* USART 1 Baud Rate 1 */
DEFC( U1BR1 , U1BR1_)
#define U1RXBUF_ (0x007E) /* USART 1 Receive Buffer */
READ_ONLY DEFC( U1RXBUF , U1RXBUF_)
#define U1TXBUF_ (0x007F) /* USART 1 Transmit Buffer */
DEFC( U1TXBUF , U1TXBUF_)
/* Alternate register names */
#define UCTL1 U1CTL /* USART 1 Control */
#define UTCTL1 U1TCTL /* USART 1 Transmit Control */
#define URCTL1 U1RCTL /* USART 1 Receive Control */
#define UMCTL1 U1MCTL /* USART 1 Modulation Control */
#define UBR01 U1BR0 /* USART 1 Baud Rate 0 */
#define UBR11 U1BR1 /* USART 1 Baud Rate 1 */
#define RXBUF1 U1RXBUF /* USART 1 Receive Buffer */
#define TXBUF1 U1TXBUF /* USART 1 Transmit Buffer */
#define UCTL1_ U1CTL_ /* USART 1 Control */
#define UTCTL1_ U1TCTL_ /* USART 1 Transmit Control */
#define URCTL1_ U1RCTL_ /* USART 1 Receive Control */
#define UMCTL1_ U1MCTL_ /* USART 1 Modulation Control */
#define UBR01_ U1BR0_ /* USART 1 Baud Rate 0 */
#define UBR11_ U1BR1_ /* USART 1 Baud Rate 1 */
#define RXBUF1_ U1RXBUF_ /* USART 1 Receive Buffer */
#define TXBUF1_ U1TXBUF_ /* USART 1 Transmit Buffer */
#define UCTL_1 U1CTL /* USART 1 Control */
#define UTCTL_1 U1TCTL /* USART 1 Transmit Control */
#define URCTL_1 U1RCTL /* USART 1 Receive Control */
#define UMCTL_1 U1MCTL /* USART 1 Modulation Control */
#define UBR0_1 U1BR0 /* USART 1 Baud Rate 0 */
#define UBR1_1 U1BR1 /* USART 1 Baud Rate 1 */
#define RXBUF_1 U1RXBUF /* USART 1 Receive Buffer */
#define TXBUF_1 U1TXBUF /* USART 1 Transmit Buffer */
#define UCTL_1_ U1CTL_ /* USART 1 Control */
#define UTCTL_1_ U1TCTL_ /* USART 1 Transmit Control */
#define URCTL_1_ U1RCTL_ /* USART 1 Receive Control */
#define UMCTL_1_ U1MCTL_ /* USART 1 Modulation Control */
#define UBR0_1_ U1BR0_ /* USART 1 Baud Rate 0 */
#define UBR1_1_ U1BR1_ /* USART 1 Baud Rate 1 */
#define RXBUF_1_ U1RXBUF_ /* USART 1 Receive Buffer */
#define TXBUF_1_ U1TXBUF_ /* USART 1 Transmit Buffer */
/************************************************************
* Timer A3
************************************************************/
#define TAIV_ (0x012E) /* Timer A Interrupt Vector Word */
READ_ONLY DEFW( TAIV , TAIV_)
#define TACTL_ (0x0160) /* Timer A Control */
DEFW( TACTL , TACTL_)
#define TACCTL0_ (0x0162) /* Timer A Capture/Compare Control 0 */
DEFW( TACCTL0 , TACCTL0_)
#define TACCTL1_ (0x0164) /* Timer A Capture/Compare Control 1 */
DEFW( TACCTL1 , TACCTL1_)
#define TACCTL2_ (0x0166) /* Timer A Capture/Compare Control 2 */
DEFW( TACCTL2 , TACCTL2_)
#define TAR_ (0x0170) /* Timer A */
DEFW( TAR , TAR_)
#define TACCR0_ (0x0172) /* Timer A Capture/Compare 0 */
DEFW( TACCR0 , TACCR0_)
#define TACCR1_ (0x0174) /* Timer A Capture/Compare 1 */
DEFW( TACCR1 , TACCR1_)
#define TACCR2_ (0x0176) /* Timer A Capture/Compare 2 */
DEFW( TACCR2 , TACCR2_)
/* Alternate register names */
#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */
#define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */
#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */
#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */
#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */
#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */
#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */
#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */
#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */
#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */
#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */
#define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */
#define TASSEL2 (0x0400) /* unused */ /* to distinguish from USART SSELx */
#define TASSEL1 (0x0200) /* Timer A clock source select 0 */
#define TASSEL0 (0x0100) /* Timer A clock source select 1 */
#define ID1 (0x0080) /* Timer A clock input devider 1 */
#define ID0 (0x0040) /* Timer A clock input devider 0 */
#define MC1 (0x0020) /* Timer A mode control 1 */
#define MC0 (0x0010) /* Timer A mode control 0 */
#define TACLR (0x0004) /* Timer A counter clear */
#define TAIE (0x0002) /* Timer A counter interrupt enable */
#define TAIFG (0x0001) /* Timer A counter interrupt flag */
#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */
#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continous up */
#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */
#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */
#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */
#define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */
#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */
#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */
#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */
#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */
#define CM1 (0x8000) /* Capture mode 1 */
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