testbench_file_adder4.vhd

加法器测试平台

entity testbench_file_adder4 is
end;

------------------------------------------------------------------------
-- testbench for 4-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all;
architecture adder4 of testbench_file_adder4 is 
    component adderN 
	generic(N : integer);
	port (a    : in std_logic_vector(N downto 1);
	      b    : in std_logic_vector(N downto 1);
	      cin  : in std_logic;
	      sum  : out std_logic_vector(N downto 1);
	      cout : out std_logic);
    end component;
    
    file adder_io: text open write_mode is "adderio";

    constant N : integer := 4;

    signal a    : std_logic_vector(N downto 1);
    signal b    : std_logic_vector(N downto 1);
    signal cin  : std_logic;
    signal sum  : std_logic_vector(N downto 1);
    signal cout : std_logic;

    -- convert a std_logic value to a character
    --
    type stdlogic_to_char_t is array(std_logic) of character;
    constant to_char : stdlogic_to_char_t := (
	'U' => 'U',
	'X' => 'X',
	'0' => '0',
	'1' => '1',
	'Z' => 'Z',
	'W' => 'W',
	'L' => 'L',
	'H' => 'H',
	'-' => '-');

    --
    -- convert a std_logic_vector to a string
    --
    function to_string(inp : std_logic_vector)
    return string
    is
	alias vec : std_logic_vector(1 to inp'length) is inp;
	variable result : string(vec'range);
    begin
	for i in vec'range loop
	    result(i) := to_char(vec(i));
	end loop;
	return result;
    end;

begin
    -- instantiate the component
    uut: adderN generic map(N)
		port map(a => a,
			 b => b,
			 cin => cin,
			 sum => sum,
			 cout => cout);
 
    -- provide stimulus and check the result
    test: process
	variable found_error : boolean := false;
	variable a1,b1,s1:bit_vector(4 downto 1);
	variable c1,cout1:bit;
	variable add1,resu:line;
    begin
    loop
        readline(input,add1);
        read(add1,a1);
        read(add1,b1);
        read(add1,c1);
        --send the input data to the adder
        a<=to_stdlogicvector(a1);
        b<=to_stdlogicvector(b1);
        cin<=to_stdulogic(c1);        

	    -- wait for the outputs to settle
	    wait for 100 ns;
	    s1:=to_bitvector(sum);
	    cout1:=to_bit(cout);
       write(resu,s1);
       write(resu,cout1);
       writeline(output,resu);

   end loop;
	assert not found_error
	  report "There were ERRORS in the test."
	  severity note;
	assert found_error
	  report "Test completed with no errors."
	  severity note;
	wait;
    end process;
end adder4;
configuration test_adder_behavioral of testbench_file_adder4 is
    for adder4
	for all: adderN 
	    use entity work.adderN(behavioral);
	end for;
    end for;
end test_adder_behavioral;