structural.vhd

加法器测试平台

ARCHITECTURE	structural	OF addern IS
    COMPONENT add_1
    PORT	(x,y,ci:in std_logic;
    sum,co:out std_logic);
    END COMPONENT;
SIGNAL c: std_logic_vector(n+1 DOWNTO 1);
BEGIN
   gen: for i in 1 to n generate
   u1: add_1 port map(a(i),b(i),c(i),sum(i),c(i+1));
   end generate;
   c(1)<=cin;
   cout<=c(n+1);
END	structural;