test_5.vhd

来自「老师给我们的vhdl源代码」· VHDL 代码 · 共 24 行

LIBRARY IEEE;                                   
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux4 IS
PORT (a,b,d0,d1,d2,d3: IN STD_LOGIC;
q: OUT STD_LOGIC);
END mux4;
ARCHITECTURE archi OF mux4 IS
SIGNAL sel:INTEGER RANGE 0 TO 3;
BEGIN
	P1:PROCESS(a,b,d0,d1,d2,d3)
		BEGIN
			    sel<=0;
				IF(a='1') THEN sel<=sel+1; 	END IF;
				IF(b='1') THEN sel<=sel+2; 	END IF;
				CASE sel IS
				WHEN 0 =>q<=d0;
				WHEN 1 =>q<=d1;
				WHEN 2=>q<=d2;
				WHEN 3 =>q<=d3;
				END CASE;
		END PROCESS P1;		
END archi;