38yimaqi.vhd

老师给我们的vhdl源代码

LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY  yimaqi3_8 IS
    PORT(A0,A1,A2: IN STD_LOGIC;
         E1,E2,E3: IN STD_LOGIC;
         O0,O1,O2,O3,O4,O5,O6,O7: OUT STD_LOGIC);
END yimaqi3_8;
ARCHITECTURE one OF yimaqi3_8 IS
    SIGNAL addr:STD_LOGIC_VECTOR(2 DOWNTO 0);
    SIGNAL Q:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL tem:INTEGER;
    BEGIN
        addr<= A2&A1&A0;
        process(addr,E1,E2,E3)
            BEGIN
                IF (E1='1' OR E2 ='1' OR E3='0') THEN Q<="11111111";
                ELSE
                CASE addr IS
                    WHEN "000"=>Q<="11111110";
                    WHEN "001"=>Q<="11111101";
                    WHEN "010"=>Q<="11111011";
                    WHEN "011"=>Q<="11110111";
                    WHEN "100"=>Q<="11101111";
                    WHEN "101"=>Q<="11011111";
                    WHEN "110"=>Q<="10111111";
                    WHEN "111"=>Q<="01111111";
                    WHEN OTHERS=>Q<="11111111";
               END CASE;
               tem<=Q'LENGTH;
     END IF;
END PROCESS;
      O7<=Q(7);O6<=Q(6);O5<=Q(5);O4<=Q(4);
      O3<=Q(3);O2<=Q(2);O1<=Q(1);O0<=Q(0);
END one;