mux4.vhd

来自「老师给我们的vhdl源代码」· VHDL 代码 · 共 22 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux4 IS
  PORT(i0,i1,i2,i3:IN STD_LOGIC;
            a:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
            q:OUT STD_LOGIC);
 END mux4;
 ARCHITECTURE behav OF mux4 IS
   SIGNAL sel:INTEGER;
    BEGIN
       WITH sel SELECT
          q<=i0 WHEN 0,
             i1 WHEN 1,
             i2 WHEN 2,
             i3 WHEN 3,
             'X'WHEN OTHERS;
          sel<=0 WHEN a="00000000"ELSE
               1 WHEN a="00000001"ELSE
               2 WHEN a="00000010"ELSE
               3 WHEN a="00000011"ELSE
               4;
     END behav;