readfile.vhd

老师给我们的vhdl源代码

LIBRARY IEEE;
USE  IEEE.STD_LOGIC_1164.ALL;
USE  IEEE.STD_LOGIC_TEXTIO.ALL;
USE  STD.TEXTIO.ALL;
ENTITY readfile IS
PORT(cs:IN STD_LOGIC;
Q1,Q2,Q3:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY;
ARCHITECTURE archi OF readfile IS
BEGIN
PROCESS(cs)
FILE cfile:TEXT;
VARIABLE aline:LINE;
VARIABLE tem1,tem2,tem3:STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
BEGIN
IF(cs='1') THEN
FILE_OPEN(cfile,"testfile.DAT",READ_MODE);
READLINE(cfile,aline);
READ(aline,tem1);
READLINE(cfile,aline);
READ(aline,tem2);
READLINE(cfile,aline);
READ(aline,tem3);
 Q1<=tem1;
 Q2<=tem2;
 Q3<=tem3;
 IF(ENDFILE(cfile)) THEN
 FILE_CLOSE(cfile);
 END IF;
 END IF;
 END PROCESS;    
 END ARCHITECTURE archi;