mux5.vhd

来自「老师给我们的vhdl源代码」· VHDL 代码 · 共 24 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL
ENTITY mux5 IS
  PORT(i0,i1,i2,i3,i4:IN STD_LOGIC;
            a:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
            q:OUT STD_LOGIC);
 END mux5;
ARCHITECTURE rtl OF mux5 IS
  SIGNAL sel:INTERGER;
  BEGIN
    WITH sel SELECT
      q<=i0 WHEN 0,
         i1 WHEN 1,
         i2 WHEN 2,
         i3 WHEN 3,
         i4 WHEN 4,
         'X' WHEN OTHERS;
      sel<=0 WHEN a="000"ELSE
           1 WHEN a="001"ELSE
           2 WHEN a="010"ELSE
           3 WHEN a="011"ELSE
           4 WHEN a="100"ELSE
           'x';
  END rtl;