property.vhd

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LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY  Property IS
    PORT(clk: IN STD_LOGIC;
         O: OUT STD_LOGIC);
END Property;


ARCHITECTURE  arch1  OF  Property  IS   ----?????????
    TYPE  cynumber  IS RANGE 3  TO  999 ;  --???DOWNTO,??????
BEGIN
	PROCESS ( clk )
	VARIABLE  d0, d1, d2, d3 :  cynumber ;
	BEGIN
		d0 :=  cynumber'LEFT ;    
		d1 :=  cynumber'RIGHT ;    
		d2 :=  cynumber'HIGH ;    
		d3 :=  cynumber'LOW ;      
		END  PROCESS ;
END  arch1 ;


-- ?????????????
ARCHITECTURE  arch2  OF  Property  IS   --?????????
TYPE  DATA_BUS  IS  ARRAY  ( 31 DOWNTO 0 )  OF  STD_LOGIC ; -- ??????? DATA_BUS
BEGIN
	PROCESS ( clk )
	VARIABLE  d0, d1, d2, d3 :  INTEGER ;
	BEGIN
		d0 :=  DATA_BUS'LEFT ;     -- d0 = 31
		d1 :=  DATA_BUS'RIGHT ;    -- d1 = 0
		d2 :=  DATA_BUS'HIGH ;     -- d2 = 31
		d3 :=  DATA_BUS'LOW ;      -- d3 = 0
    END  PROCESS ;
END  arch2 ;


ARCHITECTURE  arch3  OF  Property  IS   --????????
TYPE  cytime  IS  ( sec, min, hour, day, month, year ) ;-- ????????? cytime
SUBTYPE  reverse_cytime  IS  cytime  RANGE  month  DOWNTO  min  ;-- ?????????? reverse_cytime

SIGNAL  temp1, temp2, temp3, temp4  :  cytime ;
SIGNAL  temp5, temp6, temp7, temp8  :  cytime ;
BEGIN
	PROCESS ( clk )
	BEGIN
		temp1 <= cytime'LEFT;  -- temp1???sec,????cytime?????
		temp2 <= cytime'RIGHT;  -- temp2???year, ????cytime?????
		temp3 <= cytime'HIGH;   -- temp3???year, ????cytime????
		temp4 <= cytime'LOW;    -- temp4???sec, ????cytime????

		temp5  <=  reverse_cytime'LEFT ; 
				-- temp5???month, ?????reverse_cytime?????
		temp6  <=  reverse_cytime'RIGHT ;
					-- temp6???min, ?????reverse_cytime?????
		temp7  <=  reverse_cytime'HIGH ;
					-- temp7???month, ?????reverse_cytime????
		temp8  <=  reverse_cytime'LOW ; 
					-- temp8???min, ?????reverse_cytime????
    END  PROCESS ;
END  arch3 ;

ARCHITECTURE  arch4  OF  Property  IS  --????'LENGTH

TYPE  array_bit  IS  ARRAY  ( 0  TO  31 ) OF  BIT ; -- ???????
TYPE  array_integer  IS  ARRAY  ( 0 TO 63  ) OF  INTEGER ;
BEGIN
	PROCESS ( clk )
	VARIABLE  temp1_length, temp2_length :  INTEGER ;
	BEGIN
		temp1_length :=  array_bit'LENGTH ;     -- temp1_length = 32
		temp2_length :=  array_integer'LENGTH ;    -- temp2_length = 64
    END  PROCESS ;
END  arch4 ;