calcaute_week.vhd

来自「老师给我们的vhdl源代码」· VHDL 代码 · 共 35 行

LIBRARY IEEE ;
USE  IEEE.STD_LOGIC_1164.ALL ;
LIBRARY WORK ;
USE  WORK.my_package.ALL ;

ENTITY  calculate_cyweek  IS
PORT (  clk  : IN  STD_LOGIC) ;
END ENTITY calculate_cyweek ;

ARCHITECTURE  behavioral  OF  calculate_cyweek  IS
BEGIN
	PROCESS ( clk )
	VARIABLE  temp1,temp2,temp3,temp4 :  cyweek ;
	VARIABLE  temp5, temp6, temp7, temp8 :  reverse_cyweek ;
	BEGIN
		temp1 := cyweek'SUCC (wednesday);
		temp2 := cyweek'PRED(friday );
		temp3 := cyweek'LEFTOF(wednesday ); 
		temp4 := cyweek'RIGHTOF ( sunday ); 
		temp5 := reverse_cyweek'SUCC ( wednesday ) ; 
	
		temp6  :=  reverse_cyweek'PRED ( friday ) ;
		
		temp7  :=  reverse_cyweek'LEFTOF ( wednesday ) ; 
		
		temp8  :=  reverse_cyweek'RIGHTOF ( monday ) ;
	
    END  PROCESS ;
END  behavioral ;