decoder_3_to_8.vhd

来自「老师给我们的vhdl源代码」· VHDL 代码 · 共 29 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY decode_3_to_8 IS
   PORT (a,b,c,a0,a1,a2:IN STD_LOGIC;
               y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END decode_3_to_8;
ARCHITECTURE wl OF decode_3_to_8 IS
   SIGNAL indata: STD_LOGIC_VECTOR(2 DOWNTO 0);
   BEGIN
    indata<=c&b&a;
    PROCESS(indata,a0,a1,a2)
      BEGIN
       IF(a0='1' AND a1='0' AND a2='0') THEN
         CASE indata IS
          WHEN "000"=>y<="11111110";
          WHEN "001"=>y<="11111101";
          WHEN "010"=>y<="11111011";
          WHEN "011"=>y<="11110111";
          WHEN "100"=>y<="11101111";
          WHEN "101"=>y<="11011111";
          WHEN "110"=>y<="10111111";
          WHEN "111"=>y<="01111111";
          WHEN OTHERS=>y<="XXXXXXXX";
        END CASE;
     ELSE
      y<="11111111";
     END IF;
    END PROCESS;
   END wl;