test.vhd

来自「老师给我们的vhdl源代码」· VHDL 代码 · 共 13 行

LIBRARY IEEE;                                   
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY test  IS                                  
	PORT(din:  IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	    en:IN STD_LOGIC;
		dout:  OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
		
END ENTITY test;
ARCHITECTURE  archi_dataflow  OF test  IS              
BEGIN
       dout<= NOT din WHEN en='0' ELSE "ZZZZZZZZ";
END ARCHITECTURE  archi_dataflow;