inv.vhd

老师给我们的vhdl源代码

LIBRARY IEEE;                                   
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY inv  IS                                  
	PORT(a :  IN STD_LOGIC;
		c:   OUT  STD_LOGIC );
END ENTITY inv;
ARCHITECTURE  archi  OF inv  IS              
BEGIN
       c<= (NOT a); 
END ARCHITECTURE  archi;