behavior.vhd

老师给我们的vhdl源代码

LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY  cmux_21  IS
PORT ( data1, data2  : IN  STD_LOGIC ;
              sel :  IN  STD_LOGIC ;
               q :  OUT STD_LOGIC ) ;
END ENTITY cmux_21 ;

ARCHITECTURE  struct  OF  cmux_21  IS
COMPONENT  inv 
	PORT (  a : IN  STD_LOGIC ;
			c : OUT STD_LOGIC ) ;
END COMPONENT ;

COMPONENT  and2 
	PORT ( a, b : IN  STD_LOGIC ;
			c : OUT STD_LOGIC ) ;
END COMPONENT ;

COMPONENT  or2 
	PORT ( a, b : IN  STD_LOGIC ;
			c : OUT STD_LOGIC ) ;
END COMPONENT ;
SIGNAL  temp1, temp2, not_sel :  STD_LOGIC ;
BEGIN
	cunit1 :  inv   PORT  MAP ( sel, not_sel ) ;
	cunit2 :  and2  PORT  MAP ( not_sel, data2, temp2 ) ;
	cunit3 :  and2  PORT  MAP ( sel, data1, temp1 ) ;
	cunit4 :  or2   PORT  MAP (temp1, temp2, q ) ;
	
END ARCHITECTURE  struct ;