and2.vhd

老师给我们的vhdl源代码

LIBRARY IEEE;                                   
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY and2  IS                                  
	PORT(a ,b:  IN STD_LOGIC;
		c:   OUT  STD_LOGIC );
END ENTITY and2;
ARCHITECTURE  archi  OF and2  IS              
BEGIN
       c<= a and b; 
END ARCHITECTURE  archi;