5xuan1.vhd

来自「老师给我们的vhdl源代码」· VHDL 代码 · 共 16 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY wuxuanyi IS
    PORT(s:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
         i0,i1,i2,i3,i4: IN STD_LOGIC;
         q: OUT STD_LOGIC);
END wuxuanyi;
ARCHITECTURE one OF wuxuanyi IS
    BEGIN 
        q<=i0 WHEN s="000" ELSE
           i1 WHEN s="001" ELSE
           i2 WHEN s="010" ELSE
           i3 WHEN s="011" ELSE
           i4 WHEN s="100" ELSE
           'X';
END one;