38yimaqi1.vhd

来自「老师给我们的vhdl源代码」· VHDL 代码 · 共 30 行

LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY  yimaqi3_8 IS
    PORT(addr: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
         E1,E2,E3: IN STD_LOGIC;
         Q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END yimaqi3_8;
ARCHITECTURE one OF yimaqi3_8 IS
    SIGNAL Enable:STD_LOGIC;
    BEGIN
        Enable<=(NOT E1) AND (NOT E2) AND E3;
        process(addr,E1,E2,E3)
            BEGIN
                IF (Enable='1') THEN Q<="11111111";
                ELSE
                CASE addr IS
                    WHEN "000"=>Q<="11111110";
                    WHEN "001"=>Q<="11111101";
                    WHEN "010"=>Q<="11111011";
                    WHEN "011"=>Q<="11110111";
                    WHEN "100"=>Q<="11101111";
                    WHEN "101"=>Q<="11011111";
                    WHEN "110"=>Q<="10111111";
                    WHEN "111"=>Q<="01111111";
                    WHEN OTHERS=>Q<="11111111";
               END CASE;
     END IF;
END PROCESS;
END one;