writefile.vhd

来自「老师给我们的vhdl源代码」· VHDL 代码 · 共 26 行

LIBRARY IEEE;
USE  IEEE.STD_LOGIC_1164.ALL;
USE  IEEE.STD_LOGIC_TEXTIO.ALL;
USE  STD.TEXTIO.ALL;
ENTITY writefile IS
PORT(cs:IN STD_LOGIC;
Q1,Q2,Q3:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY;
ARCHITECTURE archi OF writefile IS
BEGIN
PROCESS(cs)
FILE cfile:TEXT;
VARIABLE aline:LINE;
VARIABLE tem1,tem2,tem3:STD_LOGIC_VECTOR(7 DOWNTO 0):="11110000";
BEGIN
IF(cs='1') THEN
FILE_OPEN(cfile,"testfile.DAT",write_mode);
WRITE(aline,tem1);
WRITELINE(cfile,aline);
IF(ENDFILE(cfile)) THEN
 FILE_CLOSE(cfile);
 END IF;
 END IF;
 END PROCESS;    
 END ARCHITECTURE archi;