📄 regsettings_infinitelink.c
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0x31, // FREQ1 Frequency control word, middle byte.
0x3B, // FREQ0 Frequency control word, low byte.
0x7B, // MDMCFG4 Modem configuration.
0x83, // MDMCFG3 Modem configuration.
0x03, // MDMCFG2 Modem configuration.
0x22, // MDMCFG1 Modem configuration.
0xF8, // MDMCFG0 Modem configuration.
0x00, // CHANNR Channel number.
0x42, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
0xB6, // FREND1 Front end RX configuration.
0x10, // FREND0 Front end TX configuration.
0x18, // MCSM0 Main Radio Control State Machine configuration.
0x1D, // FOCCFG Frequency Offset Compensation Configuration.
0x1C, // BSCFG Bit synchronization Configuration.
0xC7, // AGCCTRL2 AGC control.
0x00, // AGCCTRL1 AGC control.
0xB2, // AGCCTRL0 AGC control.
0xEA, // FSCAL3 Frequency synthesizer calibration.
0x2A, // FSCAL2 Frequency synthesizer calibration.
0x00, // FSCAL1 Frequency synthesizer calibration.
0x1F, // FSCAL0 Frequency synthesizer calibration.
0x59, // FSTEST Frequency synthesizer calibration.
0x81, // TEST2 Various test settings.
0x35, // TEST1 Various test settings.
0x09, // TEST0 Various test settings.
0x0E, // FIFOTHR RXFIFO and TXFIFO thresholds.
0x29, // IOCFG2 GDO2 output pin configuration.
0x06, // IOCFG0D GDO0 output pin configuration.
0x04, // PKTCTRL1 Packet automation control.
0x06, // PKTCTRL0 Packet automation control.
0x00, // ADDR Device address.
0xFF // PKTLEN Packet length.
};
// PATABLE (0 dBm output power)
BYTE code paTable = 0x8E;
#endif
//-------------------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------------
#ifdef FREQ_915_CC1101
// Chipcon
// Product = CC1101
// Chip version = A (VERSION = 0x04)
// Crystal accuracy = 10 ppm
// X-tal frequency = 26 MHz
// RF output power = 0 dBm
// RX filterbandwidth = 232.142857 kHz
// Deviation = 32 kHz
// Datarate = 76.766968 kBaud
// Modulation = (1) GFSK
// Manchester enable = (0) Manchester disabled
// RF Frequency = 914.999969 MHz
// Channel spacing = 199.951172 kHz
// Channel number = 0
// Optimization = -
// Sync mode = (3) 30/32 sync word bits detected
// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
// Forward Error Correction = (0) FEC disabled
// Length configuration = (2) Infinite packet length mode
// Packetlength = 255
// Preamble count = (2) 4 bytes
// Append status = 1
// Address check = (0) No address check
// FIFO autoflush = 0
// Device address = 0
// GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet
// GDO2 signal selection = (41) CHIP_RDY
RF_SETTINGS code rfSettings = {
0x08, // FSCTRL1 Frequency synthesizer control.
0x00, // FSCTRL0 Frequency synthesizer control.
0x23, // FREQ2 Frequency control word, high byte.
0x31, // FREQ1 Frequency control word, middle byte.
0x3B, // FREQ0 Frequency control word, low byte.
0x7B, // MDMCFG4 Modem configuration.
0x83, // MDMCFG3 Modem configuration.
0x13, // MDMCFG2 Modem configuration.
0x22, // MDMCFG1 Modem configuration.
0xF8, // MDMCFG0 Modem configuration.
0x00, // CHANNR Channel number.
0x42, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
0xB6, // FREND1 Front end RX configuration.
0x10, // FREND0 Front end TX configuration.
0x18, // MCSM0 Main Radio Control State Machine configuration.
0x1D, // FOCCFG Frequency Offset Compensation Configuration.
0x1C, // BSCFG Bit synchronization Configuration.
0xC7, // AGCCTRL2 AGC control.
0x00, // AGCCTRL1 AGC control.
0xB2, // AGCCTRL0 AGC control.
0xEA, // FSCAL3 Frequency synthesizer calibration.
0x2A, // FSCAL2 Frequency synthesizer calibration.
0x00, // FSCAL1 Frequency synthesizer calibration.
0x1F, // FSCAL0 Frequency synthesizer calibration.
0x59, // FSTEST Frequency synthesizer calibration.
0x81, // TEST2 Various test settings.
0x35, // TEST1 Various test settings.
0x09, // TEST0 Various test settings.
0x4E, // FIFOTHR RXFIFO and TXFIFO thresholds.
0x29, // IOCFG2 GDO2 output pin configuration.
0x06, // IOCFG0D GDO0 output pin configuration.
0x04, // PKTCTRL1 Packet automation control.
0x06, // PKTCTRL0 Packet automation control.
0x00, // ADDR Device address.
0xFF // PKTLEN Packet length.
};
// PATABLE (0 dBm output power)
BYTE code paTable = 0x8E;
#endif
//-------------------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------------
#ifdef FREQ_955_CC1100E
// Chipcon
// Product = CC1100E
// Chip version = A (VERSION = 0x05)
// Crystal accuracy = 10 ppm
// X-tal frequency = 26 MHz
// RF output power = 0 dBm
// RX filterbandwidth = 232.142857 kHz
// Deviation = 32 kHz
// Datarate = 76.766968 kBaud
// Modulation = (1) GFSK
// Manchester enable = (0) Manchester disabled
// RF Frequency = 954.999725 MHz
// Channel spacing = 199.951172 kHz
// Channel number = 0
// Optimization = -
// Sync mode = (3) 30/32 sync word bits detected
// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
// Forward Error Correction = (0) FEC disabled
// Length configuration = (2) Infinite packet length mode
// Packetlength = 255
// Preamble count = (2) 4 bytes
// Append status = 1
// Address check = (0) No address check
// FIFO autoflush = 0
// Device address = 0
// GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet
// GDO2 signal selection = (41) CHIP_RDY
RF_SETTINGS code rfSettings = {
0x08, // FSCTRL1 Frequency synthesizer control.
0x00, // FSCTRL0 Frequency synthesizer control.
0x24, // FREQ2 Frequency control word, high byte.
0xBB, // FREQ1 Frequency control word, middle byte.
0x13, // FREQ0 Frequency control word, low byte.
0x7B, // MDMCFG4 Modem configuration.
0x83, // MDMCFG3 Modem configuration.
0x13, // MDMCFG2 Modem configuration.
0x22, // MDMCFG1 Modem configuration.
0xF8, // MDMCFG0 Modem configuration.
0x00, // CHANNR Channel number.
0x42, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
0xB6, // FREND1 Front end RX configuration.
0x10, // FREND0 Front end TX configuration.
0x18, // MCSM0 Main Radio Control State Machine configuration.
0x1D, // FOCCFG Frequency Offset Compensation Configuration.
0x1C, // BSCFG Bit synchronization Configuration.
0xC7, // AGCCTRL2 AGC control.
0x00, // AGCCTRL1 AGC control.
0xB2, // AGCCTRL0 AGC control.
0xAA, // FSCAL3 Frequency synthesizer calibration.
0x0A, // FSCAL2 Frequency synthesizer calibration.
0x00, // FSCAL1 Frequency synthesizer calibration.
0x07, // FSCAL0 Frequency synthesizer calibration.
0x59, // FSTEST Frequency synthesizer calibration.
0x81, // TEST2 Various test settings.
0x35, // TEST1 Various test settings.
0x09, // TEST0 Various test settings.
0x4E, // FIFOTHR RXFIFO and TXFIFO thresholds.
0x29, // IOCFG2 GDO2 output pin configuration.
0x06, // IOCFG0D GDO0 output pin configuration.
0x04, // PKTCTRL1 Packet automation control.
0x06, // PKTCTRL0 Packet automation control.
0x00, // ADDR Device address.
0xFF // PKTLEN Packet length.
};
// PATABLE (0 dBm output power)
BYTE code paTable = 0x60;
#endif
//-------------------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------------
#ifdef FREQ_2_4
// Product = CC2500
// Chip version = E (VERSION = 0x03)
// Crystal accuracy = 10 ppm
// X-tal frequency = 26 MHz
// RF output power = 0 dBm
// RX filterbandwidth = 232.142857 kHz
// Deviation = 32 kHz
// Datarate = 76.766968 kBaud
// Modulation = (1) GFSK
// Manchester enable = (0) Manchester disabled
// RF Frequency = 2432.999908 MHz
// Channel spacing = 199.951172 kHz
// Channel number = 0
// Optimization = Sensitivity
// Sync mode = (3) 30/32 sync word bits detected
// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
// Forward Error Correction = (0) FEC disabled
// Length configuration = (2) Infinite packet length mode
// Packetlength = 255
// Preamble count = (2) 4 bytes
// Append status = 1
// Address check = (0) No address check
// FIFO autoflush = 0
// Device address = 0
// GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet
// GDO2 signal selection = (41) CHIP_RDY
RF_SETTINGS code rfSettings = {
0x08, // FSCTRL1 Frequency synthesizer control.
0x00, // FSCTRL0 Frequency synthesizer control.
0x5D, // FREQ2 Frequency control word, high byte.
0x93, // FREQ1 Frequency control word, middle byte.
0xB1, // FREQ0 Frequency control word, low byte.
0x7B, // MDMCFG4 Modem configuration.
0x83, // MDMCFG3 Modem configuration.
0x13, // MDMCFG2 Modem configuration.
0x22, // MDMCFG1 Modem configuration.
0xF8, // MDMCFG0 Modem configuration.
0x00, // CHANNR Channel number.
0x42, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
0xB6, // FREND1 Front end RX configuration.
0x10, // FREND0 Front end TX configuration.
0x18, // MCSM0 Main Radio Control State Machine configuration.
0x1D, // FOCCFG Frequency Offset Compensation Configuration.
0x1C, // BSCFG Bit synchronization Configuration.
0xC7, // AGCCTRL2 AGC control.
0x00, // AGCCTRL1 AGC control.
0xB2, // AGCCTRL0 AGC control.
0xA9, // FSCAL3 Frequency synthesizer calibration.
0x0A, // FSCAL2 Frequency synthesizer calibration.
0x00, // FSCAL1 Frequency synthesizer calibration.
0x11, // FSCAL0 Frequency synthesizer calibration.
0x59, // FSTEST Frequency synthesizer calibration.
0x88, // TEST2 Various test settings.
0x31, // TEST1 Various test settings.
0x0B, // TEST0 Various test settings.
0x0E, // FIFOTHR RXFIFO and TXFIFO thresholds.
0x29, // IOCFG2 GDO2 output pin configuration.
0x06, // IOCFG0D GDO0 output pin configuration.
0x04, // PKTCTRL1 Packet automation control.
0x06, // PKTCTRL0 Packet automation control.
0x00, // ADDR Device address.
0xFF // PKTLEN Packet length.
};
// PATABLE (0 dBm output power)
BYTE code paTable = 0xFE;
#endif
//-------------------------------------------------------------------------------------------------------
/******************************************************************************************************
* Revision history: *
*
* $Log: RegSettings_InfiniteLink.c,v $
* Revision 1.5 2007/11/23 09:28:33 a0190596
* Updated in accordance with SmartRF Studio Settings
*
* Revision 1.4 2007/06/22 13:33:44 a0190596
* Updated register settings + added CC1101 register settings
*
* Revision 1.3 2007/01/23 07:30:45 a0190596
* Changed register settings according to new characterization results
*
* Revision 1.2 2006/11/14 13:33:30 a0190596
* Changed PATABLE settings for 0 dBm
*
* Revision 1.1 2006/04/25 15:00:40 a0190596
* Initial version in CVS.
*
*
*
*
*
******************************************************************************************************/
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