pelican.c

一个关于PCI CAN开发板的windows下的驱动程序,用DDK做的,希望对做PCI CAN板的朋友有用

                for (i = 0; i < 13; i++) {
                        c = sysInByte(iobase_adr + 0x0a);
                        UrgBuf[i] = c;
                }
                sysOutByte(iobase_adr + 0x0b, 0x00);             			
		if(p!=NULL)
		  p( 0x2 );
	}  else if ((IntSrc & 0xc0) == 0x40) {
		sysOutByte(iobase_adr + 0x0f, 0xf6);
                for (i = 0; i < 13; i++) {
                        c = sysInByte(iobase_adr + 0x0e);
                        UrgBuf[i] = c;
                }
                sysOutByte(iobase_adr + 0x0f, 0x00);              			
		if(p!=NULL)
		  p( 0x3 );
	}

        //intUnlock(oldLvl);	
}

/*readout the status of sja1000*/
UINT8_T can_st(UINT8_T channel)
{
	UINT8_T c, sr_num, rd_jdg, bgn_rd, end_prp;
	UINT32_T mem_adr;
	UINT32_T timeout;
	UINT8_T c0, c1, prp_res;
	UINT8_T end_rd = 0x0;
	
	mem_adr = iobase_adr + 4* channel;
	
        switch (channel) {

                case 0:
                        sr_num = 0x01;
                        bgn_rd = 0x02;
                        end_prp = 0x03;
                        prp_res = 0xfc;
                        break;
                case 1:
                        sr_num = 0x04;
                        bgn_rd = 0x08;
                        end_prp = 0x0c;
                        prp_res = 0xf3;                                                                        
                        break;
                case 2:
                        sr_num = 0x10;
                        bgn_rd = 0x20;
                        end_prp = 0x30;
                        prp_res = 0xcf;                                                                        
                        break;
                case 3:
                        sr_num = 0x40;
                        bgn_rd = 0x80;
                        end_prp = 0xc0;
                        prp_res = 0x3f;                                                                        
                        break;
                default:
                        break;
        }
	c0 = sysInByte(iobase_adr + 0x18);
	c1 = (c0&prp_res) | sr_num;        
        
        sysOutByte(iobase_adr + 0x18, c1);        
        sysOutByte(mem_adr, REG_SR);
        
	c0 = sysInByte(iobase_adr + 0x18);
	c1 = (c0&prp_res) | end_prp;            
        
        sysOutByte(iobase_adr + 0x18, c1);
        timeout = 2000;
        do {
        	rd_jdg = sysInByte(iobase_adr + 0x18);
        	timeout--;
	}  while(((rd_jdg&end_prp) != 0x0) && timeout);
	if (0x0 == (rd_jdg&end_prp))
	{
	c0 = sysInByte(iobase_adr + 0x18);
	c1 = (c0&prp_res) | bgn_rd; 		
		
        sysOutByte(iobase_adr + 0x18, c1);
        c = sysInByte(mem_adr + 1);	

	c0 = sysInByte(iobase_adr + 0x18);
	c1 = (c0&prp_res) | end_rd; 
	
        sysOutByte(iobase_adr + 0x18, c1);	        		
	}
	else {
                logMsg("can_st:read SR faild!\n", 0, 0, 0, 0, 0, 0);		
	}	              	
	
	return c;
}

/*reset sja1000 while encounter errors*/
int can_rst(UINT8_T channel)
{
	UINT8_T rst_num, bgn_wrt, end_wrt, wrt_jdg;
	UINT8_T c, rd_jdg, prp_rd, end_prp, bgn_rd, end_rd;
	UINT32_T timeout1, timeout2;	
	UINT32_T mem_adr;
	UINT8_T reg, c0, c1, reserve,prp_res;	
	
	mem_adr = iobase_adr + 4* channel;	
	
	switch(channel) {
		case 0:
			rst_num = 0x01;
			bgn_wrt = 0x01;
			end_wrt = 0x03;
			prp_rd = 0x01;
			end_prp = 0x03;
			bgn_rd = 0x02;
			end_rd = 0x0;
			reserve = 0xfc;
			prp_res =0xfe;		
			break;
		case 1:
			rst_num = 0x02;
			bgn_wrt = 0x04;	
			end_wrt = 0x0c;	
			prp_rd = 0x04;
			end_prp = 0x0c;			
			bgn_rd = 0x08;
			end_rd = 0x0;			
			reserve = 0xf3;
			prp_res =0xfd;																	
			break;
		case 2:
			rst_num = 0x04;
			bgn_wrt = 0x10;	
			end_wrt = 0x30;
			prp_rd = 0x10;
			end_prp = 0x30;			
			bgn_rd = 0x20;
			end_rd = 0x0;			
			reserve = 0xcf;
			prp_res =0xfb;																			
			break;
		case 3:
			rst_num = 0x08;
			bgn_wrt = 0x40;
			end_wrt = 0xc0;
			prp_rd = 0x40;
			end_prp = 0xc0;			
			bgn_rd = 0x80;
			end_rd = 0x0;			
			reserve = 0x3f;
			prp_res =0xf7;																				
			break;
		default:
			break;		
	}
	
	c0 = sysInByte(iobase_adr + 0x19);
	c1 = (c0&prp_res) | rst_num;
		
        sysOutByte(iobase_adr + 0x19, c1);
        
	timeout1 = 2000;
	do {
	c0 = sysInByte(iobase_adr + 0x1a);
	c1 = (c0&reserve) | bgn_wrt; 		
		
	sysOutByte(iobase_adr + 0x1a, c1);	
	reg = REG_MOD;
	sysOutByte(mem_adr, reg);
	sysOutByte(mem_adr + 0x1, 0x01);
	
	c0 = sysInByte(iobase_adr + 0x1a);
	c1 = (c0&reserve) | end_wrt; 		
	sysOutByte(iobase_adr + 0x1a, end_wrt);

	c0 = sysInByte(iobase_adr + 0x18);
	c1 = (c0&reserve) | prp_rd; 
		
        sysOutByte(iobase_adr + 0x18, c1);        
        sysOutByte(mem_adr, REG_MOD);
        
	c0 = sysInByte(iobase_adr + 0x18);
	c1 = (c0&reserve) | end_prp;         
        sysOutByte(iobase_adr + 0x18, c1);
        timeout2 = 2000;
        do {
        	rd_jdg = sysInByte(iobase_adr + 0x18);
        	timeout2--;
	}  while(((rd_jdg&end_prp) != 0x0) && timeout2);
	if (0x0 == (rd_jdg&end_prp))
	{
	c0 = sysInByte(iobase_adr + 0x18);
	c1 = (c0&reserve) | bgn_rd; 		
		
        sysOutByte(iobase_adr + 0x18, c1);
        c = sysInByte(mem_adr + 1);
        
	c0 = sysInByte(iobase_adr + 0x18);
	c1 = (c0&reserve) | end_rd;        
        		
        sysOutByte(iobase_adr + 0x18, c1);        		
	}
	else {
                logMsg("can_rst:read MOD faild!\n", 0, 0, 0, 0, 0, 0);
                return ERROR;		
	}
        timeout1--;
	} while ((c != 0x01) && timeout1);	        
        
	timeout1 = 2000;
	do {
	c0 = sysInByte(iobase_adr + 0x1a);
	c1 = (c0&reserve) | bgn_wrt;
			
	sysOutByte(iobase_adr + 0x1a, c1);
	reg = REG_CDR;
	sysOutByte(mem_adr, reg);
	sysOutByte(mem_adr + 0x1, 0xc7);
	
	c0 = sysInByte(iobase_adr + 0x1a);
	c1 = (c0&reserve) | end_wrt;		
	sysOutByte(iobase_adr + 0x1a, c1);
	
	
	c0 = sysInByte(iobase_adr + 0x18);
	c1 = (c0&reserve) | prp_rd;
		
        sysOutByte(iobase_adr + 0x18, c1);        
        sysOutByte(mem_adr, REG_CDR);
        
	c0 = sysInByte(iobase_adr + 0x18);
	c1 = (c0&reserve) | end_prp;        
        sysOutByte(iobase_adr + 0x18, c1);
        timeout2 = 2000;
        do {
        	rd_jdg = sysInByte(iobase_adr + 0x18);
        	timeout2--;
	}  while(((rd_jdg&end_prp) != 0x0) && timeout2);
	if (0x0 == (rd_jdg&end_wrt))
	{
	c0 = sysInByte(iobase_adr + 0x18);
	c1 = (c0&reserve) | prp_rd;		
		
        sysOutByte(iobase_adr + 0x18, c1);
        c = sysInByte(mem_adr + 1);
        
	c0 = sysInByte(iobase_adr + 0x18);
	c1 = (c0&reserve) | end_rd;        		
        sysOutByte(iobase_adr + 0x18, c1);        		
	}
	else {
                logMsg("can_rst:read CDR faild!\n", 0, 0, 0, 0, 0, 0);
                return ERROR;                		
	}
        timeout1--;
	} while ((c != 0xc7) && timeout1);		
	
	timeout1 = 2000;
	do {
	c0 = sysInByte(iobase_adr + 0x1a);
	c1 = (c0&reserve) | bgn_wrt;  
			
	sysOutByte(iobase_adr + 0x1a, c1);	
	reg = REG_CMR;
	sysOutByte(mem_adr, reg);
	sysOutByte(mem_adr + 0x1, 0x0e);
	
	c0 = sysInByte(iobase_adr + 0x1a);
	c1 = (c0&reserve) | end_wrt;  		
	sysOutByte(iobase_adr + 0x1a, c1);

	c0 = sysInByte(iobase_adr + 0x18);
	c1 = (c0&reserve) | prp_rd; 
		
        sysOutByte(iobase_adr + 0x18, c1);        
        sysOutByte(mem_adr, REG_CMR);
        
	c0 = sysInByte(iobase_adr + 0x18);
	c1 = (c0&reserve) | end_prp; 
	        
        sysOutByte(iobase_adr + 0x18, c1);
        timeout2 = 2000;
        do {
        	rd_jdg = sysInByte(iobase_adr + 0x18);
        	timeout2--;
	}  while(((rd_jdg&end_prp) != 0x0) && timeout2);
	if (0x0 == (rd_jdg&end_prp))
	{
	c0 = sysInByte(iobase_adr + 0x18);
	c1 = (c0&reserve) | bgn_rd;
			
        sysOutByte(iobase_adr + 0x18, c1);
        c = sysInByte(mem_adr + 1);
        
	c0 = sysInByte(iobase_adr + 0x18);
	c1 = (c0&reserve) | end_rd;
	        		
        sysOutByte(iobase_adr + 0x18, end_rd);        		
	}
	else {
                logMsg("can_rst:read CMR faild!\n", 0, 0, 0, 0, 0, 0);
                return ERROR;		
	}
        timeout1--;
	} while ((c != 0x0e) && timeout1);			
		
	timeout1 = 2000;
	do {
	c0 = sysInByte(iobase_adr + 0x1a);
	c1 = (c0&reserve) | bgn_wrt; 		
		
	sysOutByte(iobase_adr + 0x1a, c1);	
	reg = REG_MOD;
	sysOutByte(mem_adr, reg);
	sysOutByte(mem_adr + 0x1, 0x08);
	
	c0 = sysInByte(iobase_adr + 0x1a);
	c1 = (c0&reserve) | end_wrt; 		
	sysOutByte(iobase_adr + 0x1a, end_wrt);

	c0 = sysInByte(iobase_adr + 0x18);
	c1 = (c0&reserve) | prp_rd; 
		
        sysOutByte(iobase_adr + 0x18, c1);        
        sysOutByte(mem_adr, REG_MOD);
        
	c0 = sysInByte(iobase_adr + 0x18);
	c1 = (c0&reserve) | end_prp;         
        sysOutByte(iobase_adr + 0x18, c1);
        timeout2 = 2000;
        do {
        	rd_jdg = sysInByte(iobase_adr + 0x18);
        	timeout2--;
	}  while(((rd_jdg&end_prp) != 0x0) && timeout2);
	if (0x0 == (rd_jdg&end_prp))
	{
	c0 = sysInByte(iobase_adr + 0x18);
	c1 = (c0&reserve) | bgn_rd; 		
		
        sysOutByte(iobase_adr + 0x18, c1);
        c = sysInByte(mem_adr + 1);
        
	c0 = sysInByte(iobase_adr + 0x18);
	c1 = (c0&reserve) | end_rd;        
        		
        sysOutByte(iobase_adr + 0x18, c1);        		
	}
	else {
                logMsg("can_rst:read MOD faild!\n", 0, 0, 0, 0, 0, 0);
                return ERROR;		
	}
        timeout1--;
	} while ((c != 0x08) && timeout1);			
	
	return OK;		      	
}

/*initialize sj1000 to known state*/
int can_init(UINT8_T channel,int baudrate)
{
	int index = 0;
	int busNo;	/* PCI bus number */
	int devNo;	/* PCI device number */
	int funcNo;	/* PCI function number */
	UINT32_T iobase;	/* PCI base address */
	UINT8_T reg;
	char c;
	char tx55,txaa;
	char irq;
	int i,j,k;
	char m0,m1,m2,m3;

	if ((pciFindDevice(0x32, 0x3202, index, &busNo, &devNo, &funcNo)) != OK) 
	{
		debug_printf("\nthe CAN board doesn't exist!\n");	
	} else
	{
		pciConfigInLong(busNo, devNo, funcNo, PCI_CFG_BASE_ADDRESS_3, &iobase);
		pciConfigInByte(busNo, devNo, funcNo, PCI_CFG_DEV_INT_LINE, &irq);
		iobase  &= PCI_IOBASE_MASK;
		int_lvl = irq;
		
		for (i = 0;i < 13;i++) UrgBuf[i] = 0;
		
		debug_printf("\nFind CAN board :iobase=%x irq0=%x \n", iobase, irq);
		
		iobase_adr = iobase;
		sysOutByte(iobase_adr + 0x10,0x0f);
		
		reg = REG_TEST;
		can_write(channel, reg, 0x55);
		delay(2000);
		tx55 = can_read(channel, reg);
		can_write(channel, reg, 0xaa);
		delay(2000);
		txaa = can_read(channel, reg);			
		if ((tx55 == 0x55) || ((UINT8_T)txaa == 0xaa)) {
                        debug_printf("in hardware test, channel %d# is OK\n", channel);
                } else {
                        debug_printf("in hardware test,channel %d# is ERROR\n", channel);
                        //exit(0);
						return ERROR;
                }

		reg = REG_MOD;
                do {
                        can_write(channel, reg, 0x01);
                        c = can_read(channel, reg);
                } while (!(c&0x01));
		
                reg = REG_CDR;
                do {
                        can_write(channel, reg, 0xc7);
                        c = can_read(channel, reg);
                } while ((UINT8_T) c != 0xc7);		
                
		reg = REG_IER;
                do {
                        can_write(channel, reg, 0x3);
                        c = can_read(channel, reg);
                } while (c != 0x3);
                
		
         for (j = 0; j < 13; j++)
               {
        			if (baudTable [j].rate == baudrate)    
            			{
            				reg=REG_BTR0;
            				can_write(channel,reg,(char)baudTable[j].btr0);
					        c=can_read(channel,reg);
  					        do {
     						     can_write(channel,reg,(char)baudTable[j].btr0);
     						     c=can_read(channel,reg);
  					            } while ((c&0xff) != (baudTable[j].btr0));		
					        reg=REG_BTR1;
  					        can_write(channel,reg,(char)baudTable[j].btr1);
					        c=can_read(channel,reg);

  					        do {
     						     can_write(channel,reg,(char)baudTable[j].btr1);
     						     c=can_read(channel,reg);
  					            } while ((c&0xff) != (baudTable[j].btr1));
            				break;
            			}
        	    }

	          debug_printf("\n btr0: %x   btr1: %x\n", baudTable[j].btr0, baudTable[j].btr1);

                reg = REG_ACR0;
                do {                     	
                        can_write(channel, reg, 0x10);
                        c = can_read(channel, reg);                       
                } while ((c&0xff) != 0x10);
                         
                reg = REG_ACR1;
                do {
                        can_write(channel, reg, 0x10);
                        c = can_read(channel, reg);
                } while ((c&0xff) !=0x10);
                
                reg = REG_ACR2;
                do {
                        can_write(channel, reg, 0x10);
                        c = can_read(channel, reg);
                } while ((c&0xff) != 0x10); 
                
                reg = REG_ACR3;
                do {                 	
                        can_write(channel, reg, 0x10);
                        c = can_read(channel, reg);                     
                } while ((c&0xff) != 0x10);                                                         
                                                 
                reg = REG_AMR0;
                do {
                        can_write(channel, reg, 0xFF);
                        c = can_read(channel, reg);
                } while ((c&0xff) != 0xFF);
                
                reg = REG_AMR1;
                do {
                        can_write(channel, reg, 0xFF);
                        c = can_read(channel, reg);
                } while ((c&0xff) != 0xFF);
                
                reg = REG_AMR2;
                do {
                        can_write(channel, reg, 0xFF);
                        c = can_read(channel, reg);
                } while ((c&0xff) != 0xFF); 
                
                reg = REG_AMR3;
                do {
                        can_write(channel, reg, 0xFF);
                        c = can_read(channel, reg);
                } while ((c&0xff) != 0xFF); 


                reg = REG_OCR;
                do {
                        can_write(channel, reg, 0x1a);
                        c = can_read(channel, reg);
                } while (c != 0x1a);
                
                reg = REG_MOD;
                do {
                        can_write(channel, reg, 0x08);
                        c = can_read(channel, reg);
                } while (c != 0x08);                                
		
	}

        //(void) pciIntConnect(INUM_TO_IVEC(INT_NUM_COM), CanRecvInt, NULL);
        //sysIntEnablePIC(int_lvl);

        sysOutByte(iobase_adr + 0x10, 0x0);
        sysOutByte(iobase_adr + 0x17, 0x0);
        sysOutByte(iobase_adr + 0x18, 0x0);
        sysOutByte(iobase_adr + 0x1a, 0x0);		
	
        return OK;
}