deled.vhd

来自「有关数字钟的」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
entity deled is
port(s:in std_logic_vector(3 downto 0);
	daout:out std_logic_vector(7 downto 0));
end deled;
architecture behave of deled is
begin
PROCESS
BEGIN
CASE s IS
when "0000"=>daout<="11111100";
when "0001"=>daout<="00001100";
when "0010"=>daout<="11011010";
when "0011"=>daout<="11110010";
when "0100"=>daout<="01100110";
when "0101"=>daout<="10110110";
when "0110"=>daout<="10111110";
when "0111"=>daout<="11100000";
when "1000"=>daout<="11111110";
when "1001"=>daout<="11110110";
when others=>daout<="11001111";
end CASE;
END PROCESS;
end behave;