📄 cout60_v.rpt
字号:
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\d_clock\cout60_v.rpt
cout60_v
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 7 CLK
Device-Specific Information: d:\d_clock\cout60_v.rpt
cout60_v
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 7 CLRN
Device-Specific Information: d:\d_clock\cout60_v.rpt
cout60_v
** EQUATIONS **
CLK : INPUT;
CLRN : INPUT;
Da0 : INPUT;
Da1 : INPUT;
Da2 : INPUT;
Da3 : INPUT;
Db0 : INPUT;
Db1 : INPUT;
Db2 : INPUT;
EN : INPUT;
LDN : INPUT;
-- Node name is 'Qa0'
-- Equation name is 'Qa0', type is output
Qa0 = tmpa0~189;
-- Node name is 'Qa1'
-- Equation name is 'Qa1', type is output
Qa1 = tmpa1~189;
-- Node name is 'Qa2'
-- Equation name is 'Qa2', type is output
Qa2 = tmpa2~189;
-- Node name is 'Qa3'
-- Equation name is 'Qa3', type is output
Qa3 = tmpa3~189;
-- Node name is 'Qb0'
-- Equation name is 'Qb0', type is output
Qb0 = tmpb0~187;
-- Node name is 'Qb1'
-- Equation name is 'Qb1', type is output
Qb1 = tmpb1~187;
-- Node name is 'Qb2'
-- Equation name is 'Qb2', type is output
Qb2 = tmpb2~187;
-- Node name is 'RCO'
-- Equation name is 'RCO', type is output
RCO = _LC1_B23;
-- Node name is ':43' = 'tmpa0~189'
-- Equation name is 'tmpa0~189', location is LC1_B16, type is buried.
tmpa0~189 = DFFE( _EQ001, GLOBAL( CLK), GLOBAL( CLRN), VCC, VCC);
_EQ001 = !EN & LDN & tmpa0~189
# EN & LDN & !tmpa0~189
# Da0 & !LDN;
-- Node name is ':42' = 'tmpa1~189'
-- Equation name is 'tmpa1~189', location is LC1_B21, type is buried.
tmpa1~189 = DFFE( _EQ002, GLOBAL( CLK), GLOBAL( CLRN), VCC, VCC);
_EQ002 = _LC3_B21 & LDN
# Da1 & !LDN;
-- Node name is ':41' = 'tmpa2~189'
-- Equation name is 'tmpa2~189', location is LC6_B16, type is buried.
tmpa2~189 = DFFE( _EQ003, GLOBAL( CLK), GLOBAL( CLRN), VCC, VCC);
_EQ003 = _LC3_B16 & LDN
# Da2 & !LDN;
-- Node name is ':40' = 'tmpa3~189'
-- Equation name is 'tmpa3~189', location is LC5_B16, type is buried.
tmpa3~189 = DFFE( _EQ004, GLOBAL( CLK), GLOBAL( CLRN), VCC, VCC);
_EQ004 = _LC8_B16 & LDN
# Da3 & !LDN;
-- Node name is ':46' = 'tmpb0~187'
-- Equation name is 'tmpb0~187', location is LC7_B21, type is buried.
tmpb0~187 = DFFE( _EQ005, GLOBAL( CLK), GLOBAL( CLRN), VCC, VCC);
_EQ005 = _LC2_B21 & LDN
# Db0 & !LDN;
-- Node name is ':45' = 'tmpb1~187'
-- Equation name is 'tmpb1~187', location is LC3_B23, type is buried.
tmpb1~187 = DFFE( _EQ006, GLOBAL( CLK), GLOBAL( CLRN), VCC, VCC);
_EQ006 = _LC5_B23 & LDN
# Db1 & !LDN;
-- Node name is ':44' = 'tmpb2~187'
-- Equation name is 'tmpb2~187', location is LC2_B23, type is buried.
tmpb2~187 = DFFE( _EQ007, GLOBAL( CLK), GLOBAL( CLRN), VCC, VCC);
_EQ007 = _LC7_B23 & LDN
# Db2 & !LDN;
-- Node name is '|LPM_ADD_SUB:128|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B16', type is buried
_LC4_B16 = LCELL( _EQ008);
_EQ008 = tmpa0~189 & tmpa1~189 & tmpa2~189;
-- Node name is '|LPM_ADD_SUB:128|addcore:adder|:68' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC2_B16', type is buried
_LC2_B16 = LCELL( _EQ009);
_EQ009 = !tmpa1~189 & tmpa2~189
# !tmpa0~189 & tmpa2~189
# tmpa0~189 & tmpa1~189 & !tmpa2~189;
-- Node name is ':83'
-- Equation name is '_LC7_B16', type is buried
_LC7_B16 = LCELL( _EQ010);
_EQ010 = tmpa0~189 & !tmpa1~189 & !tmpa2~189 & tmpa3~189;
-- Node name is ':162'
-- Equation name is '_LC6_B23', type is buried
_LC6_B23 = LCELL( _EQ011);
_EQ011 = _LC7_B16 & tmpb0~187 & tmpb1~187 & !tmpb2~187
# !tmpb0~187 & tmpb2~187
# !_LC7_B16 & tmpb2~187;
-- Node name is ':168'
-- Equation name is '_LC4_B23', type is buried
_LC4_B23 = LCELL( _EQ012);
_EQ012 = !_LC7_B16 & tmpb1~187
# !tmpb0~187 & tmpb1~187
# _LC7_B16 & tmpb0~187 & !tmpb1~187 & !tmpb2~187;
-- Node name is ':186'
-- Equation name is '_LC8_B16', type is buried
_LC8_B16 = LCELL( _EQ013);
_EQ013 = !_LC4_B16 & !_LC7_B16 & tmpa3~189
# EN & _LC4_B16 & !_LC7_B16 & !tmpa3~189
# !EN & tmpa3~189;
-- Node name is ':198'
-- Equation name is '_LC3_B16', type is buried
_LC3_B16 = LCELL( _EQ014);
_EQ014 = EN & _LC2_B16 & !_LC7_B16
# !EN & tmpa2~189;
-- Node name is ':207'
-- Equation name is '_LC3_B21', type is buried
_LC3_B21 = LCELL( _EQ015);
_EQ015 = !_LC7_B16 & !tmpa0~189 & tmpa1~189
# EN & !_LC7_B16 & tmpa0~189 & !tmpa1~189
# !EN & tmpa1~189;
-- Node name is ':225'
-- Equation name is '_LC7_B23', type is buried
_LC7_B23 = LCELL( _EQ016);
_EQ016 = EN & _LC6_B23
# !EN & tmpb2~187;
-- Node name is ':234'
-- Equation name is '_LC5_B23', type is buried
_LC5_B23 = LCELL( _EQ017);
_EQ017 = EN & _LC4_B23
# !EN & tmpb1~187;
-- Node name is ':243'
-- Equation name is '_LC2_B21', type is buried
_LC2_B21 = LCELL( _EQ018);
_EQ018 = !_LC7_B16 & tmpb0~187
# EN & _LC7_B16 & !tmpb0~187
# !EN & tmpb0~187;
-- Node name is '~278~1'
-- Equation name is '~278~1', location is LC8_B23, type is buried.
-- synthesized logic cell
_LC8_B23 = LCELL( _EQ019);
_EQ019 = tmpb0~187 & tmpb2~187;
-- Node name is ':278'
-- Equation name is '_LC1_B23', type is buried
_LC1_B23 = LCELL( _EQ020);
_EQ020 = EN & _LC8_B23 & tmpa0~189 & tmpa3~189;
Project Information d:\d_clock\cout60_v.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,454K
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