📄 cout12_v.rpt
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Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\d_clock\cout12_v.rpt
cout12_v
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 4/ 96( 4%) 0/ 48( 0%) 5/ 48( 10%) 3/16( 18%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\d_clock\cout12_v.rpt
cout12_v
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 clk
Device-Specific Information: d:\d_clock\cout12_v.rpt
cout12_v
** EQUATIONS **
clk : INPUT;
clrn : INPUT;
da0 : INPUT;
da1 : INPUT;
da2 : INPUT;
da3 : INPUT;
db : INPUT;
en : INPUT;
ldn : INPUT;
-- Node name is ':150' = 'a0'
-- Equation name is 'a0', location is LC3_C13, type is buried.
a0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = clrn & _LC6_C13 & ldn
# clrn & da0 & !ldn;
-- Node name is ':149' = 'a1'
-- Equation name is 'a1', location is LC7_C13, type is buried.
a1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = clrn & _LC8_C13 & ldn
# clrn & da1 & !ldn;
-- Node name is ':148' = 'a2'
-- Equation name is 'a2', location is LC8_C22, type is buried.
a2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = clrn & _LC3_C22 & ldn
# clrn & da2 & !ldn;
-- Node name is ':147' = 'a3'
-- Equation name is 'a3', location is LC1_C22, type is buried.
a3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = clrn & _LC5_C22 & ldn
# clrn & da3 & !ldn;
-- Node name is ':96' = 'b'
-- Equation name is 'b', location is LC4_C13, type is buried.
b = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = clrn & _LC5_C13 & ldn
# clrn & db & !ldn;
-- Node name is 'qa0'
-- Equation name is 'qa0', type is output
qa0 = a0;
-- Node name is 'qa1'
-- Equation name is 'qa1', type is output
qa1 = a1;
-- Node name is 'qa2'
-- Equation name is 'qa2', type is output
qa2 = a2;
-- Node name is 'qa3'
-- Equation name is 'qa3', type is output
qa3 = a3;
-- Node name is 'qb'
-- Equation name is 'qb', type is output
qb = b;
-- Node name is '|lpm_add_sub:157|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C22', type is buried
_LC2_C22 = LCELL( _EQ006);
_EQ006 = a0 & a1;
-- Node name is '|lpm_add_sub:157|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_C22', type is buried
_LC4_C22 = LCELL( _EQ007);
_EQ007 = a0 & a1 & a2;
-- Node name is '~81~1'
-- Equation name is '~81~1', location is LC1_C13, type is buried.
-- synthesized logic cell
!_LC1_C13 = _LC1_C13~NOT;
_LC1_C13~NOT = LCELL( _EQ008);
_EQ008 = a0 & !a1 & !a2;
-- Node name is '~94~1'
-- Equation name is '~94~1', location is LC5_C13, type is buried.
-- synthesized logic cell
_LC5_C13 = LCELL( _EQ009);
_EQ009 = b & _LC1_C13
# b & !en
# a3 & !b & en & !_LC1_C13;
-- Node name is '~118~1'
-- Equation name is '~118~1', location is LC2_C13, type is buried.
-- synthesized logic cell
_LC2_C13 = LCELL( _EQ010);
_EQ010 = en & _LC1_C13
# !a3 & !b & en;
-- Node name is ':127'
-- Equation name is '_LC5_C22', type is buried
_LC5_C22 = LCELL( _EQ011);
_EQ011 = a3 & _LC2_C13 & !_LC4_C22
# !a3 & _LC2_C13 & _LC4_C22
# a3 & !en;
-- Node name is ':128'
-- Equation name is '_LC3_C22', type is buried
_LC3_C22 = LCELL( _EQ012);
_EQ012 = a2 & _LC2_C13 & !_LC2_C22
# !a2 & _LC2_C13 & _LC2_C22
# a2 & !en;
-- Node name is ':129'
-- Equation name is '_LC8_C13', type is buried
_LC8_C13 = LCELL( _EQ013);
_EQ013 = !a0 & a1 & _LC2_C13
# a0 & !a1 & _LC2_C13
# a1 & !en;
-- Node name is ':130'
-- Equation name is '_LC6_C13', type is buried
_LC6_C13 = LCELL( _EQ014);
_EQ014 = a0 & !en
# !a0 & en;
Project Information d:\d_clock\cout12_v.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,961K
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