cout12_v.v

来自「d_clck的VHDL语言编程」· Verilog 代码 · 共 55 行

module cout12_v(clrn,clk,ldn,en,da,db,qa,qb);
  input clrn,clk,ldn,en;
  input[3:0] da;
  input  db;
  output[3:0] qa;
  output qb;

  reg[3:0] a;
  reg  b;

  always @(posedge clk or negedge ldn)
      begin
        if(~clrn)
          begin
           a=4'b0000;
            b='b0;
          end
         
        else if(~ldn) 
            begin
             a<=da;
             b<=db;
            end 
          else if(en)
            begin 
                if(a==4'b1001)  
                     begin
                      a=4'b0000;
                     b=b+1;
                     end 
                else if((a==4'b0001)&(b=='b1))
                     begin
                      a=4'b0000;
                    b='b0;
                     end
                else 
                     begin  
                   a=a+1; 
                     end
            end
       end
      assign qa=a;
      assign qb=b;
   endmodule