cout60_v.vhd

d_clck的VHDL语言编程

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cout60_v IS
   PORT(
      CLRN,LDN,EN,CLK  : IN STD_LOGIC;
      Da   : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
      Db   : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
      Qa   : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
      Qb   : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
      RCO  : OUT STD_LOGIC
       );
    END cout60_v;
   ARCHITECTURE a OF cout60_v IS
    BEGIN 
      PROCESS(CLK)
        VARIABLE tmpa:STD_LOGIC_VECTOR(3 DOWNTO 0);
        VARIABLE tmpb:STD_LOGIC_VECTOR(2 DOWNTO 0);
      BEGIN
        IF CLRN='0' THEN tmpb:="000";tmpa:="0000";
        ELSE IF(CLK'EVENT AND CLK='1') THEN
             IF LDN='0' THEN tmpa:=Da;tmpb:=Db;
             ELSIF EN='1' THEN
                IF tmpa="1001" THEN
                    tmpa:="0000";
                    IF tmpb="101" THEN tmpb:="000";
                    ELSE tmpb:=tmpb+1;
                    END IF;
                ELSE tmpa:=tmpa+1;
                END IF;

              END IF;
            END IF;
          END IF;
            Qa<=tmpa;Qb<=tmpb;
            RCO<=tmpb(0) AND tmpb(2) AND tmpa(0) AND tmpa(3) AND EN;
          END PROCESS;
        END a;