seven_v.v

来自「d_clck的VHDL语言编程」· Verilog 代码 · 共 22 行

module seven_v(d,s);
input[3:0] d;
output[0:6] s;
reg[0:6] s;
always
	begin
    	case(d)
			0:	s=7'b1111110;
			1:	s=7'b0000110;
			2:	s=7'b1101101;
			3:	s=7'b1111001;
			4:	s=7'b0110011;
			5:	s=7'b1011011;
			6:	s=7'b1011111;
			7:	s=7'b1110000;
			8:	s=7'b1111111;
			9:	s=7'b1111011;
			default:	s=7'b0000000;
		endcase
	end
endmodule