divided.vhd

来自「d_clck的VHDL语言编程」· VHDL 代码 · 共 32 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY divided IS 
PORT(CLKI : IN STD_LOGIC; 
     CLKO : OUT STD_LOGIC); 
END divided; 

ARCHITECTURE one OF divided IS 
SIGNAL count : STD_LOGIC_VECTOR(3 DOWNTO 0); 
SIGNAL clk_temp : STD_LOGIC; 

BEGIN 
  PROCESS(CLKI, count) 
  BEGIN 
    IF (CLKI'event AND CLKI='1') THEN 
      IF(count  = "1001") THEN 
         count <= "0000";       
         clk_temp <= NOT (clk_temp); 
      ELSE 
      count <= count +1; 
     END IF ; 
   END IF ; 
  END PROCESS; 

  CLKO <= clk_temp; 

END one;