📄 d_clock.rpt
字号:
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 8 0 0 0 0 1 8 0 0 0 0 0 0 0 0 0 0 6 0 0 8 8 0 0 0 39/0
Total: 8 0 8 6 0 1 15 7 0 8 1 0 0 0 1 0 2 6 8 0 8 8 8 2 6 103/0
Device-Specific Information: d:\d_clock\d_clock.rpt
d_clock
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
1 - - - -- INPUT G 0 0 0 0 clk
7 - - - 03 INPUT 0 0 0 9 i0
6 - - - 04 INPUT 0 0 0 5 i1
5 - - - 05 INPUT 0 0 0 5 i2
3 - - - 12 INPUT 0 0 0 3 i3
11 - - - 01 INPUT 0 0 0 26 ldn
10 - - - 01 INPUT 0 0 0 6 s0
9 - - - 02 INPUT 0 0 0 6 s1
8 - - - 03 INPUT 0 0 0 6 s2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\d_clock\d_clock.rpt
d_clock
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
16 - - A -- OUTPUT 0 1 0 0 qha0
17 - - A -- OUTPUT 0 1 0 0 qha1
18 - - A -- OUTPUT 0 1 0 0 qha2
19 - - A -- OUTPUT 0 1 0 0 qha3
21 - - B -- OUTPUT 0 1 0 0 qha4
22 - - B -- OUTPUT 0 1 0 0 qha5
23 - - B -- OUTPUT 0 1 0 0 qha6
24 - - B -- OUTPUT 0 1 0 0 qhb0
78 - - - 24 OUTPUT 0 1 0 0 qhb1
79 - - - 24 OUTPUT 0 1 0 0 qhb2
80 - - - 23 OUTPUT 0 1 0 0 qhb3
83 - - - 13 OUTPUT 0 0 0 0 qhb4
52 - - - 19 OUTPUT 0 0 0 0 qhb5
81 - - - 22 OUTPUT 0 0 0 0 qhb6
53 - - - 20 OUTPUT 0 1 0 0 qma0
54 - - - 21 OUTPUT 0 1 0 0 qma1
58 - - C -- OUTPUT 0 1 0 0 qma2
59 - - C -- OUTPUT 0 1 0 0 qma3
60 - - C -- OUTPUT 0 1 0 0 qma4
61 - - C -- OUTPUT 0 1 0 0 qma5
62 - - C -- OUTPUT 0 1 0 0 qma6
25 - - B -- OUTPUT 0 1 0 0 qmb0
27 - - C -- OUTPUT 0 1 0 0 qmb1
28 - - C -- OUTPUT 0 1 0 0 qmb2
29 - - C -- OUTPUT 0 1 0 0 qmb3
30 - - C -- OUTPUT 0 1 0 0 qmb4
35 - - - 06 OUTPUT 0 1 0 0 qmb5
36 - - - 07 OUTPUT 0 1 0 0 qmb6
38 - - - 10 OUTPUT 0 1 0 0 qsa0
39 - - - 11 OUTPUT 0 1 0 0 qsa1
47 - - - 14 OUTPUT 0 1 0 0 qsa2
48 - - - 15 OUTPUT 0 1 0 0 qsa3
49 - - - 16 OUTPUT 0 1 0 0 qsa4
50 - - - 17 OUTPUT 0 1 0 0 qsa5
51 - - - 18 OUTPUT 0 1 0 0 qsa6
65 - - B -- OUTPUT 0 1 0 0 qsb0
66 - - B -- OUTPUT 0 1 0 0 qsb1
67 - - B -- OUTPUT 0 1 0 0 qsb2
69 - - A -- OUTPUT 0 1 0 0 qsb3
70 - - A -- OUTPUT 0 1 0 0 qsb4
71 - - A -- OUTPUT 0 1 0 0 qsb5
72 - - A -- OUTPUT 0 1 0 0 qsb6
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\d_clock\d_clock.rpt
d_clock
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - A 07 AND2 0 2 0 3 |cout12_v:12|lpm_add_sub:157|addcore:adder|:55
- 5 - A 07 AND2 0 2 0 1 |cout12_v:12|lpm_add_sub:157|addcore:adder|:59
- 6 - A 08 AND2 2 1 0 1 |cout12_v:12|:25
- 8 - A 03 OR2 ! 0 4 0 2 |cout12_v:12|:27
- 8 - A 04 AND2 s 3 0 0 4 |cout12_v:12|~43~1
- 3 - A 24 OR2 s 0 4 0 4 |cout12_v:12|~93~1
- 2 - A 24 DFFE s 2 3 1 0 |cout12_v:12|b~1 (|cout12_v:12|~96~1)
- 1 - A 24 DFFE s 2 3 1 0 |cout12_v:12|b~2 (|cout12_v:12|~96~2)
- 6 - A 24 DFFE s 2 3 1 0 |cout12_v:12|b~3 (|cout12_v:12|~96~3)
- 5 - A 24 DFFE 2 3 1 2 |cout12_v:12|b (|cout12_v:12|:96)
- 4 - A 24 OR2 s 0 3 0 3 |cout12_v:12|~120~1
- 7 - A 07 OR2 0 4 0 1 |cout12_v:12|:127
- 3 - A 07 OR2 0 4 0 1 |cout12_v:12|:128
- 4 - A 08 OR2 0 4 0 1 |cout12_v:12|:129
- 6 - A 07 DFFE 2 3 0 10 |cout12_v:12|a3 (|cout12_v:12|:147)
- 4 - A 07 DFFE 2 3 0 11 |cout12_v:12|a2 (|cout12_v:12|:148)
- 3 - A 08 DFFE 2 3 0 10 |cout12_v:12|a1 (|cout12_v:12|:149)
- 5 - A 08 DFFE 1 3 0 10 |cout12_v:12|a0 (|cout12_v:12|:150)
- 5 - A 10 AND2 0 2 0 3 |COUT60_V:9|LPM_ADD_SUB:128|addcore:adder|:55
- 2 - A 10 DFFE 2 3 0 10 |COUT60_V:9|tmpa3~189 (|COUT60_V:9|:40)
- 6 - A 10 DFFE 0 4 0 9 |COUT60_V:9|tmpa2~189 (|COUT60_V:9|:41)
- 3 - A 10 DFFE 0 4 0 8 |COUT60_V:9|tmpa1~189 (|COUT60_V:9|:42)
- 2 - A 08 DFFE 2 2 0 10 |COUT60_V:9|tmpa0~189 (|COUT60_V:9|:43)
- 3 - A 22 DFFE 2 3 0 10 |COUT60_V:9|tmpb2~187 (|COUT60_V:9|:44)
- 2 - A 22 DFFE 2 3 0 9 |COUT60_V:9|tmpb1~187 (|COUT60_V:9|:45)
- 4 - A 22 DFFE 1 3 0 10 |COUT60_V:9|tmpb0~187 (|COUT60_V:9|:46)
- 2 - A 18 OR2 ! 0 4 0 4 |COUT60_V:9|:83
- 7 - A 22 OR2 0 4 0 1 |COUT60_V:9|:162
- 6 - A 22 OR2 0 4 0 1 |COUT60_V:9|:168
- 1 - A 22 AND2 s 1 1 0 3 |COUT60_V:9|~194~1
- 8 - A 10 OR2 0 4 0 1 |COUT60_V:9|:194
- 7 - A 10 AND2 2 1 0 1 |COUT60_V:9|:202
- 4 - A 10 AND2 2 1 0 1 |COUT60_V:9|:211
- 5 - A 22 AND2 2 1 0 1 |COUT60_V:9|:247
- 5 - A 18 OR2 ! 0 4 0 8 |COUT60_V:9|:276
- 2 - C 21 AND2 0 2 0 3 |COUT60_V:11|LPM_ADD_SUB:128|addcore:adder|:55
- 7 - C 20 OR2 0 3 0 1 |COUT60_V:11|LPM_ADD_SUB:128|addcore:adder|:69
- 2 - C 20 DFFE 2 3 0 11 |COUT60_V:11|tmpa3~189 (|COUT60_V:11|:40)
- 3 - C 20 DFFE 2 3 0 10 |COUT60_V:11|tmpa2~189 (|COUT60_V:11|:41)
- 1 - C 20 DFFE 2 3 0 9 |COUT60_V:11|tmpa1~189 (|COUT60_V:11|:42)
- 8 - A 08 DFFE 1 3 0 10 |COUT60_V:11|tmpa0~189 (|COUT60_V:11|:43)
- 2 - C 01 DFFE 2 3 0 11 |COUT60_V:11|tmpb2~187 (|COUT60_V:11|:44)
- 8 - C 01 DFFE 2 3 0 10 |COUT60_V:11|tmpb1~187 (|COUT60_V:11|:45)
- 1 - C 01 DFFE 2 3 0 11 |COUT60_V:11|tmpb0~187 (|COUT60_V:11|:46)
- 8 - C 21 OR2 ! 0 4 0 6 |COUT60_V:11|:83
- 6 - C 01 OR2 0 4 0 1 |COUT60_V:11|:162
- 4 - C 01 OR2 0 4 0 1 |COUT60_V:11|:168
- 8 - C 20 OR2 0 4 0 1 |COUT60_V:11|:186
- 6 - C 20 OR2 0 4 0 1 |COUT60_V:11|:198
- 5 - C 20 OR2 0 4 0 1 |COUT60_V:11|:207
- 1 - A 08 AND2 2 1 0 1 |COUT60_V:11|:220
- 7 - C 01 OR2 0 3 0 1 |COUT60_V:11|:225
- 5 - C 01 OR2 0 3 0 1 |COUT60_V:11|:234
- 3 - C 01 OR2 0 3 0 1 |COUT60_V:11|:243
- 6 - C 07 AND2 s 0 3 0 1 |COUT60_V:11|~278~1
- 2 - C 07 AND2 0 3 0 5 |COUT60_V:11|:278
- 4 - A 04 AND2 ! 3 0 0 4 |demulti4_1:10|:54
- 7 - A 04 AND2 ! 3 0 0 3 |demulti4_1:10|:65
- 1 - A 04 AND2 ! 3 0 0 4 |demulti4_1:10|:75
- 6 - A 04 AND2 ! 3 0 0 3 |demulti4_1:10|:88
- 5 - A 04 AND2 ! 3 0 0 4 |demulti4_1:10|:98
- 6 - C 17 DFFE + 0 3 0 1 |DIVIDED:7|count3 (|DIVIDED:7|:3)
- 5 - C 17 DFFE + 0 3 0 2 |DIVIDED:7|count2 (|DIVIDED:7|:4)
- 4 - C 17 DFFE + 0 2 0 3 |DIVIDED:7|count1 (|DIVIDED:7|:5)
- 1 - C 17 DFFE + 0 0 0 4 |DIVIDED:7|count0 (|DIVIDED:7|:6)
- 3 - C 17 DFFE + 0 1 0 22 |DIVIDED:7|clk_temp (|DIVIDED:7|:7)
- 2 - C 17 OR2 ! 0 4 0 3 |DIVIDED:7|:25
- 1 - A 10 OR2 0 4 1 0 |seven_v:31|:151
- 1 - A 11 OR2 0 4 1 0 |seven_v:31|:152
- 1 - A 14 OR2 0 4 1 0 |seven_v:31|:153
- 4 - A 16 OR2 0 4 1 1 |seven_v:31|:154
- 1 - A 16 OR2 0 4 1 0 |seven_v:31|:155
- 6 - A 18 OR2 0 4 1 0 |seven_v:31|:156
- 7 - A 18 OR2 0 4 1 0 |seven_v:31|:157
- 8 - A 22 OR2 0 3 1 0 |seven_v:32|:151
- 3 - A 23 OR2 0 3 1 0 |seven_v:32|:152
- 1 - A 18 OR2 0 3 1 0 |seven_v:32|:153
- 8 - A 23 OR2 0 3 1 0 |seven_v:32|:154
- 8 - A 18 OR2 0 3 1 0 |seven_v:32|:155
- 4 - A 18 OR2 0 3 1 0 |seven_v:32|:156
- 3 - A 18 OR2 0 3 1 0 |seven_v:32|:157
- 4 - C 20 OR2 0 4 1 0 |seven_v:33|:151
- 6 - C 21 OR2 0 4 1 0 |seven_v:33|:152
- 7 - C 21 OR2 0 4 1 0 |seven_v:33|:153
- 5 - C 21 OR2 0 4 1 1 |seven_v:33|:154
- 4 - C 21 OR2 0 4 1 0 |seven_v:33|:155
- 3 - C 21 OR2 0 4 1 0 |seven_v:33|:156
- 1 - C 21 OR2 0 4 1 0 |seven_v:33|:157
- 8 - C 07 OR2 0 3 1 0 |seven_v:34|:151
- 1 - C 07 OR2 0 3 1 0 |seven_v:34|:152
- 3 - C 07 OR2 0 3 1 0 |seven_v:34|:153
- 5 - C 07 OR2 0 3 1 0 |seven_v:34|:154
- 7 - C 07 OR2 0 3 1 0 |seven_v:34|:155
- 2 - C 06 OR2 0 3 1 0 |seven_v:34|:156
- 4 - C 07 OR2 0 3 1 0 |seven_v:34|:157
- 6 - A 03 OR2 ! 0 4 0 2 |seven_v:35|:24
- 1 - A 07 OR2 0 4 1 0 |seven_v:35|:151
- 3 - A 03 OR2 0 4 1 0 |seven_v:35|:152
- 5 - A 03 OR2 0 4 1 0 |seven_v:35|:153
- 7 - A 03 OR2 0 4 1 1 |seven_v:35|:154
- 1 - A 03 OR2 0 4 1 0 |seven_v:35|:155
- 2 - A 03 OR2 0 4 1 0 |seven_v:35|:156
- 4 - A 03 OR2 0 4 1 0 |seven_v:35|:157
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\d_clock\d_clock.rpt
d_clock
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 22/ 96( 22%) 14/ 48( 29%) 8/ 48( 16%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
B: 1/ 96( 1%) 4/ 48( 8%) 3/ 48( 6%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 12/ 96( 12%) 9/ 48( 18%) 11/ 48( 22%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 5/24( 20%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
04: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\d_clock\d_clock.rpt
d_clock
** CLOCK SIGNALS **
Type Fan-out Name
DFF 23 |DIVIDED:7|clk_temp
INPUT 5 clk
Device-Specific Information: d:\d_clock\d_clock.rpt
d_clock
** EQUATIONS **
clk : INPUT;
i0 : INPUT;
i1 : INPUT;
i2 : INPUT;
i3 : INPUT;
ldn : INPUT;
s0 : INPUT;
s1 : INPUT;
s2 : INPUT;
-- Node name is 'qha0'
-- Equation name is 'qha0', type is output
qha0 = _LC1_A7;
-- Node name is 'qha1'
-- Equation name is 'qha1', type is output
qha1 = _LC3_A3;
-- Node name is 'qha2'
-- Equation name is 'qha2', type is output
qha2 = _LC5_A3;
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