📄 d_clock.rpt
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Project Information d:\d_clock\d_clock.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 04/06/2009 01:18:15
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
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a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
d_clock EPF10K10LI84-4 9 42 0 0 0 % 103 17 %
User Pins: 9 42 0
Project Information d:\d_clock\d_clock.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
d_clock@1 clk
d_clock@7 i0
d_clock@6 i1
d_clock@5 i2
d_clock@3 i3
d_clock@11 ldn
d_clock@16 qha0
d_clock@17 qha1
d_clock@18 qha2
d_clock@19 qha3
d_clock@21 qha4
d_clock@22 qha5
d_clock@23 qha6
d_clock@53 qma0
d_clock@54 qma1
d_clock@58 qma2
d_clock@59 qma3
d_clock@60 qma4
d_clock@61 qma5
d_clock@62 qma6
d_clock@25 qmb0
d_clock@27 qmb1
d_clock@28 qmb2
d_clock@29 qmb3
d_clock@30 qmb4
d_clock@35 qmb5
d_clock@36 qmb6
d_clock@38 qsa0
d_clock@39 qsa1
d_clock@47 qsa2
d_clock@48 qsa3
d_clock@49 qsa4
d_clock@50 qsa5
d_clock@51 qsa6
d_clock@65 qsb0
d_clock@66 qsb1
d_clock@67 qsb2
d_clock@69 qsb3
d_clock@70 qsb4
d_clock@71 qsb5
d_clock@72 qsb6
d_clock@10 s0
d_clock@9 s1
d_clock@8 s2
Project Information d:\d_clock\d_clock.rpt
** FILE HIERARCHY **
|divided:7|
|divided:7|lpm_add_sub:56|
|divided:7|lpm_add_sub:56|addcore:adder|
|divided:7|lpm_add_sub:56|altshift:result_ext_latency_ffs|
|divided:7|lpm_add_sub:56|altshift:carry_ext_latency_ffs|
|divided:7|lpm_add_sub:56|altshift:oflow_ext_latency_ffs|
|cout60_v:9|
|cout60_v:9|lpm_add_sub:99|
|cout60_v:9|lpm_add_sub:99|addcore:adder|
|cout60_v:9|lpm_add_sub:99|altshift:result_ext_latency_ffs|
|cout60_v:9|lpm_add_sub:99|altshift:carry_ext_latency_ffs|
|cout60_v:9|lpm_add_sub:99|altshift:oflow_ext_latency_ffs|
|cout60_v:9|lpm_add_sub:128|
|cout60_v:9|lpm_add_sub:128|addcore:adder|
|cout60_v:9|lpm_add_sub:128|altshift:result_ext_latency_ffs|
|cout60_v:9|lpm_add_sub:128|altshift:carry_ext_latency_ffs|
|cout60_v:9|lpm_add_sub:128|altshift:oflow_ext_latency_ffs|
|cout60_v:11|
|cout60_v:11|lpm_add_sub:99|
|cout60_v:11|lpm_add_sub:99|addcore:adder|
|cout60_v:11|lpm_add_sub:99|altshift:result_ext_latency_ffs|
|cout60_v:11|lpm_add_sub:99|altshift:carry_ext_latency_ffs|
|cout60_v:11|lpm_add_sub:99|altshift:oflow_ext_latency_ffs|
|cout60_v:11|lpm_add_sub:128|
|cout60_v:11|lpm_add_sub:128|addcore:adder|
|cout60_v:11|lpm_add_sub:128|altshift:result_ext_latency_ffs|
|cout60_v:11|lpm_add_sub:128|altshift:carry_ext_latency_ffs|
|cout60_v:11|lpm_add_sub:128|altshift:oflow_ext_latency_ffs|
|demulti4_1:10|
|cout12_v:12|
|cout12_v:12|lpm_add_sub:156|
|cout12_v:12|lpm_add_sub:156|addcore:adder|
|cout12_v:12|lpm_add_sub:156|altshift:result_ext_latency_ffs|
|cout12_v:12|lpm_add_sub:156|altshift:carry_ext_latency_ffs|
|cout12_v:12|lpm_add_sub:156|altshift:oflow_ext_latency_ffs|
|cout12_v:12|lpm_add_sub:157|
|cout12_v:12|lpm_add_sub:157|addcore:adder|
|cout12_v:12|lpm_add_sub:157|altshift:result_ext_latency_ffs|
|cout12_v:12|lpm_add_sub:157|altshift:carry_ext_latency_ffs|
|cout12_v:12|lpm_add_sub:157|altshift:oflow_ext_latency_ffs|
|seven_v:31|
|seven_v:36|
|seven_v:35|
|seven_v:34|
|seven_v:33|
|seven_v:32|
Device-Specific Information: d:\d_clock\d_clock.rpt
d_clock
***** Logic for device 'd_clock' compiled without errors.
Device: EPF10K10LI84-4
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
Device-Specific Information: d:\d_clock\d_clock.rpt
d_clock
** ERROR SUMMARY **
Info: Chip 'd_clock' in device 'EPF10K10LI84-4' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
^
C
O
N
V G G G F
C N N N _ ^
C D D q D q q q q # D n
l I I c I h I h h h h T O C
d s s s i i i N i N l N b N b b b b C N E
n 0 1 2 0 1 2 T 3 T k T 4 T 6 3 2 1 K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | RESERVED
^nCE | 14 72 | qsb6
#TDI | 15 71 | qsb5
qha0 | 16 70 | qsb4
qha1 | 17 69 | qsb3
qha2 | 18 68 | GNDINT
qha3 | 19 67 | qsb2
VCCINT | 20 66 | qsb1
qha4 | 21 65 | qsb0
qha5 | 22 EPF10K10LI84-4 64 | RESERVED
qha6 | 23 63 | VCCINT
qhb0 | 24 62 | qma6
qmb0 | 25 61 | qma5
GNDINT | 26 60 | qma4
qmb1 | 27 59 | qma3
qmb2 | 28 58 | qma2
qmb3 | 29 57 | #TMS
qmb4 | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | qma1
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ q q R q q V G G G G V G q q q q q q q
C n m m E s s C N N N N C N s s s s s h m
C C b b S a a C D D D D C D a a a a a b a
I O 5 6 E 0 1 I I I I I I I 2 3 4 5 6 5 0
N N R N N N N N N N
T F V T T T T T T T
I E
G D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\d_clock\d_clock.rpt
d_clock
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A3 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 0/2 0/2 4/22( 18%)
A4 6/ 8( 75%) 2/ 8( 25%) 5/ 8( 62%) 0/2 0/2 3/22( 13%)
A7 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 10/22( 45%)
A8 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 10/22( 45%)
A10 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 9/22( 40%)
A11 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
A14 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
A16 2/ 8( 25%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
A18 8/ 8(100%) 5/ 8( 62%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
A22 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 7/22( 31%)
A23 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A24 6/ 8( 75%) 4/ 8( 50%) 1/ 8( 12%) 1/2 0/2 7/22( 31%)
C1 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 8/22( 36%)
C6 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
C7 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 0/2 0/2 6/22( 27%)
C17 6/ 8( 75%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 0/22( 0%)
C20 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 11/22( 50%)
C21 8/ 8(100%) 1/ 8( 12%) 7/ 8( 87%) 0/2 0/2 4/22( 18%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 50/53 ( 94%)
Total logic cells used: 103/576 ( 17%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.53/4 ( 88%)
Total fan-in: 364/2304 ( 15%)
Total input pins required: 9
Total input I/O cell registers required: 0
Total output pins required: 42
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 103
Total flipflops required: 27
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 8/ 576 ( 1%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 8 6 0 0 7 7 0 8 1 0 0 0 1 0 2 0 8 0 0 0 8 2 6 64/0
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