⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 demulti4_1.rpt

📁 d_clck的VHDL语言编程
💻 RPT
📖 第 1 页 / 共 2 页
字号:
         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
20:      2/24(  8%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                         d:\d_clock\demulti4_1.rpt
demulti4_1

** EQUATIONS **

I0       : INPUT;
I1       : INPUT;
I2       : INPUT;
I3       : INPUT;
S0       : INPUT;
S1       : INPUT;
S2       : INPUT;

-- Node name is 'HA0' from file "demulti4_1.tdf" line 23, column 10
-- Equation name is 'HA0', type is output 
HA0      =  _LC2_C20;

-- Node name is 'HA1' from file "demulti4_1.tdf" line 23, column 10
-- Equation name is 'HA1', type is output 
HA1      =  _LC7_B1;

-- Node name is 'HA2' from file "demulti4_1.tdf" line 23, column 10
-- Equation name is 'HA2', type is output 
HA2      =  _LC4_B1;

-- Node name is 'HA3' from file "demulti4_1.tdf" line 23, column 10
-- Equation name is 'HA3', type is output 
HA3      =  _LC5_A1;

-- Node name is 'HB' from file "demulti4_1.tdf" line 23, column 19
-- Equation name is 'HB', type is output 
HB       =  _LC7_C20;

-- Node name is 'MA0' from file "demulti4_1.tdf" line 22, column 10
-- Equation name is 'MA0', type is output 
MA0      =  _LC1_C20;

-- Node name is 'MA1' from file "demulti4_1.tdf" line 22, column 10
-- Equation name is 'MA1', type is output 
MA1      =  _LC6_B1;

-- Node name is 'MA2' from file "demulti4_1.tdf" line 22, column 10
-- Equation name is 'MA2', type is output 
MA2      =  _LC3_B1;

-- Node name is 'MA3' from file "demulti4_1.tdf" line 22, column 10
-- Equation name is 'MA3', type is output 
MA3      =  _LC6_C20;

-- Node name is 'MB0' from file "demulti4_1.tdf" line 22, column 21
-- Equation name is 'MB0', type is output 
MB0      =  _LC5_C20;

-- Node name is 'MB1' from file "demulti4_1.tdf" line 22, column 21
-- Equation name is 'MB1', type is output 
MB1      =  _LC1_B1;

-- Node name is 'MB2' from file "demulti4_1.tdf" line 22, column 21
-- Equation name is 'MB2', type is output 
MB2      =  _LC8_B1;

-- Node name is 'SA0' from file "demulti4_1.tdf" line 21, column 10
-- Equation name is 'SA0', type is output 
SA0      =  _LC3_C20;

-- Node name is 'SA1' from file "demulti4_1.tdf" line 21, column 10
-- Equation name is 'SA1', type is output 
SA1      =  _LC5_B1;

-- Node name is 'SA2' from file "demulti4_1.tdf" line 21, column 10
-- Equation name is 'SA2', type is output 
SA2      =  _LC3_A1;

-- Node name is 'SA3' from file "demulti4_1.tdf" line 21, column 10
-- Equation name is 'SA3', type is output 
SA3      =  _LC8_C20;

-- Node name is 'SB0' from file "demulti4_1.tdf" line 21, column 21
-- Equation name is 'SB0', type is output 
SB0      =  _LC4_C20;

-- Node name is 'SB1' from file "demulti4_1.tdf" line 21, column 21
-- Equation name is 'SB1', type is output 
SB1      =  _LC2_B1;

-- Node name is 'SB2' from file "demulti4_1.tdf" line 21, column 21
-- Equation name is 'SB2', type is output 
SB2      =  _LC1_A1;

-- Node name is ':56' from file "demulti4_1.tdf" line 9, column 17
-- Equation name is '_LC3_C20', type is buried 
_LC3_C20 = LCELL( _EQ001);
  _EQ001 =  I0 & !S0 & !S1 & !S2;

-- Node name is ':58' from file "demulti4_1.tdf" line 9, column 17
-- Equation name is '_LC5_B1', type is buried 
_LC5_B1  = LCELL( _EQ002);
  _EQ002 =  I1 & !S0 & !S1 & !S2;

-- Node name is ':60' from file "demulti4_1.tdf" line 9, column 17
-- Equation name is '_LC3_A1', type is buried 
_LC3_A1  = LCELL( _EQ003);
  _EQ003 =  I2 & !S0 & !S1 & !S2;

-- Node name is ':62' from file "demulti4_1.tdf" line 9, column 17
-- Equation name is '_LC8_C20', type is buried 
_LC8_C20 = LCELL( _EQ004);
  _EQ004 =  I3 & !S0 & !S1 & !S2;

-- Node name is ':68' from file "demulti4_1.tdf" line 11, column 17
-- Equation name is '_LC4_C20', type is buried 
_LC4_C20 = LCELL( _EQ005);
  _EQ005 =  I0 &  S0 & !S1 & !S2;

-- Node name is ':70' from file "demulti4_1.tdf" line 11, column 17
-- Equation name is '_LC2_B1', type is buried 
_LC2_B1  = LCELL( _EQ006);
  _EQ006 =  I1 &  S0 & !S1 & !S2;

-- Node name is ':72' from file "demulti4_1.tdf" line 11, column 17
-- Equation name is '_LC1_A1', type is buried 
_LC1_A1  = LCELL( _EQ007);
  _EQ007 =  I2 &  S0 & !S1 & !S2;

-- Node name is ':78' from file "demulti4_1.tdf" line 13, column 17
-- Equation name is '_LC1_C20', type is buried 
_LC1_C20 = LCELL( _EQ008);
  _EQ008 =  I0 & !S0 &  S1 & !S2;

-- Node name is ':80' from file "demulti4_1.tdf" line 13, column 17
-- Equation name is '_LC6_B1', type is buried 
_LC6_B1  = LCELL( _EQ009);
  _EQ009 =  I1 & !S0 &  S1 & !S2;

-- Node name is ':82' from file "demulti4_1.tdf" line 13, column 17
-- Equation name is '_LC3_B1', type is buried 
_LC3_B1  = LCELL( _EQ010);
  _EQ010 =  I2 & !S0 &  S1 & !S2;

-- Node name is ':84' from file "demulti4_1.tdf" line 13, column 17
-- Equation name is '_LC6_C20', type is buried 
_LC6_C20 = LCELL( _EQ011);
  _EQ011 =  I3 & !S0 &  S1 & !S2;

-- Node name is ':91' from file "demulti4_1.tdf" line 15, column 17
-- Equation name is '_LC5_C20', type is buried 
_LC5_C20 = LCELL( _EQ012);
  _EQ012 =  I0 &  S0 &  S1 & !S2;

-- Node name is ':93' from file "demulti4_1.tdf" line 15, column 17
-- Equation name is '_LC1_B1', type is buried 
_LC1_B1  = LCELL( _EQ013);
  _EQ013 =  I1 &  S0 &  S1 & !S2;

-- Node name is ':95' from file "demulti4_1.tdf" line 15, column 17
-- Equation name is '_LC8_B1', type is buried 
_LC8_B1  = LCELL( _EQ014);
  _EQ014 =  I2 &  S0 &  S1 & !S2;

-- Node name is ':101' from file "demulti4_1.tdf" line 17, column 17
-- Equation name is '_LC2_C20', type is buried 
_LC2_C20 = LCELL( _EQ015);
  _EQ015 =  I0 & !S0 & !S1 &  S2;

-- Node name is ':103' from file "demulti4_1.tdf" line 17, column 17
-- Equation name is '_LC7_B1', type is buried 
_LC7_B1  = LCELL( _EQ016);
  _EQ016 =  I1 & !S0 & !S1 &  S2;

-- Node name is ':105' from file "demulti4_1.tdf" line 17, column 17
-- Equation name is '_LC4_B1', type is buried 
_LC4_B1  = LCELL( _EQ017);
  _EQ017 =  I2 & !S0 & !S1 &  S2;

-- Node name is ':107' from file "demulti4_1.tdf" line 17, column 17
-- Equation name is '_LC5_A1', type is buried 
_LC5_A1  = LCELL( _EQ018);
  _EQ018 =  I3 & !S0 & !S1 &  S2;

-- Node name is ':114' from file "demulti4_1.tdf" line 19, column 11
-- Equation name is '_LC7_C20', type is buried 
_LC7_C20 = LCELL( _EQ019);
  _EQ019 =  I0 &  S0 & !S1 &  S2;



Project Information                                  d:\d_clock\demulti4_1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 18,867K

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -