option.inc

2440 CPU 的boot loader 引导代码

;===========================================
; NAME: option.inc
; DESC: Configuration options for .S files
; HISTORY:
; 02.28.2002: ver 0.0
;===========================================

;Start address of each stacks,
_STACK_BASEADDRESS	EQU 0x31ff8000
;removed by finey 20060720 for 32M SDRAM		_STACK_BASEADDRESS	EQU 0x33ff8000
_MMUTT_STARTADDRESS	EQU 0x31ff8000
;removed by finey 20060720 for 32M SDRAM		_MMUTT_STARTADDRESS	EQU 0x33ff8000
_ISR_STARTADDRESS	EQU 0x31ffff00
;removed by finey 20060720 for 32M SDRAM		_ISR_STARTADDRESS	EQU 0x33ffff00

;edyeh
;_STACK_BASEADDRESS	EQU 0x33F72000
;_MMUTT_STARTADDRESS	EQU 0x33F72000
;_ISR_STARTADDRESS	EQU 0x33F72000



;The location of image
UTBaseAddress  EQU	0x30000000
;CEBaseAddress  EQU	0x32040000
;CEBaseAddress  EQU	0x30201000	;r08
;CEBaseAddress  EQU	0x30200000	;r09
CEBaseAddress  EQU 0x30000000	;r11 qiang11

	GBLL 	PLL_ON_START  
PLL_ON_START	SETL 	{TRUE}


	GBLL	ENDIAN_CHANGE
ENDIAN_CHANGE	SETL	{FALSE}

	GBLA	ENTRY_BUS_WIDTH
ENTRY_BUS_WIDTH	SETA	16	


;BUSWIDTH = 16,32
	GBLA    BUSWIDTH	;max. bus width for the GPIO configuration
BUSWIDTH	SETA    32


	GBLA	FCLK
;FCLK		SETA	50000000
FCLK		SETA	399650000	;fax0511
;FCLK		SETA	296352000

    [	FCLK = 20000000	
M_MDIV	EQU	0x20	;Fin=12.0MHz Fout=30.0MHz
M_PDIV	EQU	0x4
M_SDIV	EQU	0x2
    ]

    [	FCLK = 30000000	
M_MDIV	EQU	0x34	;Fin=12.0MHz Fout=30.0MHz
M_PDIV	EQU	0x4
M_SDIV	EQU	0x2
    ]

    [	FCLK = 50000000	
M_MDIV	EQU	0x5c	;Fin=12.0MHz Fout=50.0MHz
M_PDIV	EQU	0x4
M_SDIV	EQU	0x2
    ]

    [	FCLK = 60000000	
M_MDIV	EQU	0x70	;Fin=12.0MHz Fout=60.0MHz
M_PDIV	EQU	0x4
M_SDIV	EQU	0x2
    ]

    [	FCLK = 70000000
M_MDIV	EQU	0x84	;Fin=12.0MHz Fout=70.0MHz
M_PDIV	EQU	0x4
M_SDIV	EQU	0x2
    ]

    [	FCLK = 75000000	
M_MDIV	EQU	0x8e	;Fin=12.0MHz Fout=75.0MHz
M_PDIV	EQU	0x4
M_SDIV	EQU	0x2
    ]

;;luo01_0905 start
    [ FCLK = 296352000
M_MDIV		EQU	0x61   ;97	;Fin=16.9344MHz
M_PDIV		EQU	1
M_SDIV		EQU	2		; 2440A

    ]
    [ FCLK = 399650000
M_MDIV		EQU	0x6e   ;Fin=16.9344MHz Fout=399.65Mhz
M_PDIV		EQU	3
M_SDIV		EQU	1		; 2440A

    ]    
    
;;luo02_0906 UCLK = 48000000
U_MDIV		EQU	60	;Fin=16.9344MHz Fout=48MHz
U_PDIV		EQU	4
U_SDIV		EQU	2

CLKDIV_VAL	EQU	7	; 0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4, 4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6.

;;luo01_0905 ended
	END