xinhaohebing.mdl
来自「利用matlab/simulink 实现两路信号合并」· MDL 代码 · 共 984 行 · 第 1/2 页
MDL
984 行
}
PropName "Components"
}
Name "Configuration"
CurrentDlgPage "Solver"
}
PropName "ConfigurationSets"
}
Simulink.ConfigSet {
$PropName "ActiveConfigurationSet"
$ObjectID 1
}
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType Clock
DisplayTime off
}
Block {
BlockType EnablePort
StatesWhenEnabling "held"
ShowOutputPort off
ZeroCross on
}
Block {
BlockType Fcn
Expr "sin(u[1])"
SampleTime "-1"
}
Block {
BlockType SignalConversion
OverrideOpt off
}
Block {
BlockType Inport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
OutMin "[]"
OutMax "[]"
DataType "auto"
OutDataType "fixdt(1,16,0)"
OutScaling "[]"
OutDataTypeStr "Inherit: auto"
SignalType "auto"
SamplingMode "auto"
LatchByDelayingOutsideSignal off
LatchByCopyingInsideSignal off
Interpolate on
}
Block {
BlockType Logic
Operator "AND"
Inputs "2"
IconShape "rectangular"
AllPortsSameDT on
OutDataTypeMode "Logical (see Configuration Parameters: Optimization)"
LogicDataType "uint(8)"
OutDataTypeStr "Inherit: Logical (see Configuration Parameters: Optimization)"
SampleTime "-1"
}
Block {
BlockType Outport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
OutMin "[]"
OutMax "[]"
DataType "auto"
OutDataType "fixdt(1,16,0)"
OutScaling "[]"
OutDataTypeStr "Inherit: auto"
SignalType "auto"
SamplingMode "auto"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType Scope
ModelBased off
TickLabels "OneTimeTick"
ZoomMode "on"
Grid "on"
TimeRange "auto"
YMin "-5"
YMax "5"
SaveToWorkspace off
SaveName "ScopeData"
LimitDataPoints on
MaxDataPoints "5000"
Decimation "1"
SampleInput off
SampleTime "-1"
}
Block {
BlockType "S-Function"
FunctionName "system"
SFunctionModules "''"
PortCounts "[]"
SFunctionDeploymentMode off
}
Block {
BlockType SubSystem
ShowPortLabels "FromPortIcon"
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
TreatAsAtomicUnit off
CheckFcnCallInpInsideContextMsg off
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
CollapseMode "All dimensions"
CollapseDim "1"
InputSameDT on
AccumDataTypeStr "Inherit: Inherit via internal rule"
OutMin "[]"
OutMax "[]"
OutDataTypeMode "Same as first input"
OutDataType "fixdt(1,16,0)"
OutScaling "[]"
OutDataTypeStr "Inherit: Same as first input"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Merge
Inputs "2"
InitialOutput "[]"
AllowUnequalInputPortWidths off
InputPortOffsets "[]"
}
Block {
BlockType DiscretePulseGenerator
PulseType "Sample based"
TimeSource "Use simulation time"
Amplitude "1"
Period "2"
PulseWidth "1"
PhaseDelay "0"
SampleTime "1"
VectorParams1D on
}
Block {
BlockType Lookup
InputValues "[-4:5]"
Table " rand(1,10)-0.5"
LookUpMeth "Interpolation-Extrapolation"
OutMin "[]"
OutMax "[]"
OutDataTypeMode "Same as input"
OutDataType "fixdt(1,16,0)"
OutScaling "[]"
OutDataTypeStr "Inherit: Same as input"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
LUTDesignTableMode "Redesign Table"
LUTDesignDataSource "Block Dialog"
LUTDesignFunctionName "sqrt(x)"
LUTDesignUseExistingBP on
LUTDesignRelError "0.01"
LUTDesignAbsError "1e-6"
}
Block {
BlockType Sin
SineType "Time based"
TimeSource "Use simulation time"
Amplitude "1"
Bias "0"
Frequency "1"
Phase "0"
Samples "10"
Offset "0"
SampleTime "-1"
VectorParams1D on
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
UseDisplayTextAsClickCallback off
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "xinhaohebing"
Location [2, 74, 1022, 721]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType SubSystem
Name "Enabled\nSubsystem"
Ports [1, 1, 1]
Position [245, 44, 345, 86]
TreatAsAtomicUnit on
MinAlgLoopOccurrences off
PropExecContextOutsideSubsystem off
RTWSystemCode "Auto"
FunctionWithSeparateData off
Opaque off
RequestExecContextInheritance off
MaskHideContents off
System {
Name "Enabled\nSubsystem"
Location [421, 301, 919, 601]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [110, 103, 140, 117]
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Block {
BlockType EnablePort
Name "Enable"
Ports []
Position [235, 40, 255, 60]
}
Block {
BlockType Outport
Name "Out1"
Position [360, 103, 390, 117]
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Line {
SrcBlock "In1"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "Enabled\nSubsystem1"
Ports [1, 1, 1]
Position [245, 204, 345, 246]
TreatAsAtomicUnit on
MinAlgLoopOccurrences off
PropExecContextOutsideSubsystem off
RTWSystemCode "Auto"
FunctionWithSeparateData off
Opaque off
RequestExecContextInheritance off
MaskHideContents off
System {
Name "Enabled\nSubsystem1"
Location [421, 301, 919, 601]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [110, 103, 140, 117]
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Block {
BlockType EnablePort
Name "Enable"
Ports []
Position [235, 20, 255, 40]
}
Block {
BlockType Outport
Name "Out1"
Position [360, 103, 390, 117]
IconDisplay "Port number"
OutDataType "sfix(16)"
OutScaling "2^0"
}
Line {
SrcBlock "In1"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
}
}
Block {
BlockType Logic
Name "Logical\nOperator"
Ports [1, 1]
Position [265, 124, 295, 156]
Operator "NOT"
Inputs "1"
AllPortsSameDT off
OutDataTypeMode "boolean"
OutDataTypeStr "boolean"
}
Block {
BlockType Merge
Name "Merge"
Ports [2, 1]
Position [390, 50, 430, 90]
}
Block {
BlockType DiscretePulseGenerator
Name "Pulse\nGenerator"
Ports [0, 1]
Position [115, 123, 160, 157]
PulseType "Time based"
Period "10"
PulseWidth "50"
}
Block {
BlockType Reference
Name "Repeating\nSequence"
Ports [0, 1]
Position [115, 207, 165, 253]
SourceBlock "simulink/Sources/Repeating\nSequence"
SourceType "Repeating table"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
rep_seq_t "[0 1]"
rep_seq_y "[0 2]"
}
Block {
BlockType Scope
Name "Scope2"
Ports [1]
Position [475, 114, 505, 146]
Floating off
Location [62, 143, 509, 373]
Open on
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
TimeRange "20"
YMin "-2"
YMax "2"
SaveName "ScopeData2"
DataFormat "StructureWithTime"
SampleTime "0"
}
Block {
BlockType Sin
Name "Sine Wave"
Ports [0, 1]
Position [110, 37, 160, 83]
Frequency "pi"
SampleTime "0"
}
Line {
SrcBlock "Sine Wave"
SrcPort 1
Points [65, 0]
DstBlock "Enabled\nSubsystem"
DstPort 1
}
Line {
Labels [1, 0]
SrcBlock "Pulse\nGenerator"
SrcPort 1
Points [25, 0]
Branch {
DstBlock "Logical\nOperator"
DstPort 1
}
Branch {
Points [0, -135; 105, 0]
DstBlock "Enabled\nSubsystem"
DstPort enable
}
}
Line {
SrcBlock "Enabled\nSubsystem"
SrcPort 1
Points [0, -5]
DstBlock "Merge"
DstPort 1
}
Line {
SrcBlock "Enabled\nSubsystem1"
SrcPort 1
Points [25, 0]
DstBlock "Merge"
DstPort 2
}
Line {
SrcBlock "Merge"
SrcPort 1
Points [25, 0]
DstBlock "Scope2"
DstPort 1
}
Line {
SrcBlock "Repeating\nSequence"
SrcPort 1
Points [60, 0]
DstBlock "Enabled\nSubsystem1"
DstPort 1
}
Line {
SrcBlock "Logical\nOperator"
SrcPort 1
Points [50, 0; 0, 49]
DstBlock "Enabled\nSubsystem1"
DstPort enable
}
}
}
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