drive.vhd

关于一款线阵CCD TCD1206UD 的驱动设计

library ieee;
use ieee.std_logic_1164.all;
entity drive is
   port(clk: in std_logic;  
        qr:out std_logic;
        q1:out std_logic;
        q2:out std_logic;
        SH:out std_logic;
        SP:out std_logic);
end drive;
architecture beh of drive is
signal count1:integer range 0 to 4;
signal count2:integer range 0 to 109;
signal count3:integer;
signal qr1,qr2:std_logic;
signal q1a: std_logic;
signal sp1:std_logic;
signal sh1:std_logic;
signal qc:std_logic;
begin
process(clk)
     begin
    if(clk'event and clk='1') then 
       if(count1=4) then count1<=0;
       else count1<=count1+1;
          if(count1=0) then qr1<='1';
          else qr1<='0';
          end if;
       end if;
    end if;
   qr<=qr1;
   end process;
process(qr1)
    begin
    if(qr1='0' and qr1'event) then
       q1a<= not q1a;
    end if;
    q1<=q1a;
    q2<= not q1a;
    end process;
process(clk)
    begin
    if(clk'event and clk='1') then
        qr2<=qr1;
    end if;
    sp1<=qr2;
    SP<=qr2;
    end process;
 process(clk) 
    begin
    if(clk'event and clk='1') then
       if(count2=109) then count2<=0;
       else count2<=count2+1;
         if(count2<=4)  then sh1<='1';
         else sh1<='0';
         end if;
       end if;
    end if;
    SH<=sh1;
    end process;
process(sh1,sp1)
    begin
     if(sh1='0') then
       if(sp1'event and sp1='1') then
          count3<=count3+1;
            if(count3<=9 and count3>=3) then qc<='1';
            else qc<='0';
            end if;
       end if;
     end if;
    QC<=qc;
   end process;
end beh;