c_k.sim.vwf

来自「基于VDHL的38译码器的实现与58分频器的实现 FPGA主芯片：Cyclon」· VWF 代码 · 共 213 行

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	SIMULATION_TIME = 1000000.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 10.0;
	GRID_DUTY_CYCLE = 50;
}

SIGNAL("c_out")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("CLK")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

TRANSITION_LIST("c_out")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 10004.886;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 2.379;
		LEVEL 0 FOR 20000.0;
		LEVEL 1 FOR 9997.621;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 2.379;
		LEVEL 0 FOR 19999.373;
		LEVEL 1 FOR 9998.248;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 2.379;
		LEVEL 0 FOR 20000.0;
		LEVEL 1 FOR 9997.621;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 10000.0;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 1.752;
		LEVEL 0 FOR 0.627;
		LEVEL 1 FOR 9997.621;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 2.379;
		LEVEL 0 FOR 20000.0;
		LEVEL 1 FOR 9997.621;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 2.379;
		LEVEL 0 FOR 19999.373;
		LEVEL 1 FOR 9998.248;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 2.379;
		LEVEL 0 FOR 20000.0;
		LEVEL 1 FOR 9997.621;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 10000.0;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 1.752;
		LEVEL 0 FOR 0.627;
		LEVEL 1 FOR 9997.621;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 2.379;
		LEVEL 0 FOR 20000.0;
		LEVEL 1 FOR 9997.621;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 2.379;
		LEVEL 0 FOR 19999.373;
		LEVEL 1 FOR 9998.248;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 2.379;
		LEVEL 0 FOR 20000.0;
		LEVEL 1 FOR 9997.621;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 10000.0;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 1.752;
		LEVEL 0 FOR 0.627;
		LEVEL 1 FOR 9997.621;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 2.379;
		LEVEL 0 FOR 20000.0;
		LEVEL 1 FOR 9997.621;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 2.379;
		LEVEL 0 FOR 19999.373;
		LEVEL 1 FOR 9998.248;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 2.379;
		LEVEL 0 FOR 20000.0;
		LEVEL 1 FOR 9997.621;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 10000.0;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 1.752;
		LEVEL 0 FOR 0.627;
		LEVEL 1 FOR 9997.621;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 2.379;
		LEVEL 0 FOR 20000.0;
		LEVEL 1 FOR 9997.621;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 2.379;
		LEVEL 0 FOR 19999.373;
		LEVEL 1 FOR 9998.248;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 2.379;
		LEVEL 0 FOR 20000.0;
		LEVEL 1 FOR 9997.621;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 10000.0;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 1.752;
		LEVEL 0 FOR 0.627;
		LEVEL 1 FOR 9997.621;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 2.379;
		LEVEL 0 FOR 20000.0;
		LEVEL 1 FOR 9997.621;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 2.379;
		LEVEL 0 FOR 19999.373;
		LEVEL 1 FOR 9998.248;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 2.379;
		LEVEL 0 FOR 20000.0;
		LEVEL 1 FOR 9997.621;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 10000.0;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 1.752;
		LEVEL 0 FOR 0.627;
		LEVEL 1 FOR 9997.621;
		LEVEL 0 FOR 10000.0;
		LEVEL 1 FOR 2.379;
		LEVEL 0 FOR 19992.735;
	}
}

TRANSITION_LIST("CLK")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 10000.0;
		NODE
		{
			REPEAT = 49;
			LEVEL 0 FOR 10000.0;
			LEVEL 1 FOR 10000.0;
		}
		LEVEL 0 FOR 10000.0;
	}
}

DISPLAY_LINE
{
	CHANNEL = "c_out";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "CLK";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 1;
	TREE_LEVEL = 0;
}

TIME_BAR
{
	TIME = 17825;
	MASTER = TRUE;
}
;