c_k.tan.qmsg

基于VDHL的38译码器的实现与58分频器的实现 FPGA主芯片：CycloneII EP2C35F672C6

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK c_out CNT\[1\] 7.318 ns register " "Info: tco from clock \"CLK\" to destination pin \"c_out\" through register \"CNT\[1\]\" is 7.318 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.676 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.676 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_P2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 2; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "c_k.vhd" "" { Text "D:/EDA/实验二/06601143-06601159/58/c_k.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLK~clkctrl 2 COMB CLKCTRL_G3 3 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "c_k.vhd" "" { Text "D:/EDA/实验二/06601143-06601159/58/c_k.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.022 ns) + CELL(0.537 ns) 2.676 ns CNT\[1\] 3 REG LCFF_X1_Y18_N7 3 " "Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.676 ns; Loc. = LCFF_X1_Y18_N7; Fanout = 3; REG Node = 'CNT\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.559 ns" { CLK~clkctrl CNT[1] } "NODE_NAME" } } { "c_k.vhd" "" { Text "D:/EDA/实验二/06601143-06601159/58/c_k.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.40 % ) " "Info: Total cell delay = 1.536 ns ( 57.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.140 ns ( 42.60 % ) " "Info: Total interconnect delay = 1.140 ns ( 42.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.676 ns" { CLK CLK~clkctrl CNT[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.676 ns" { CLK CLK~combout CLK~clkctrl CNT[1] } { 0.000ns 0.000ns 0.118ns 1.022ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "c_k.vhd" "" { Text "D:/EDA/实验二/06601143-06601159/58/c_k.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.392 ns + Longest register pin " "Info: + Longest register to pin delay is 4.392 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT\[1\] 1 REG LCFF_X1_Y18_N7 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y18_N7; Fanout = 3; REG Node = 'CNT\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CNT[1] } "NODE_NAME" } } { "c_k.vhd" "" { Text "D:/EDA/实验二/06601143-06601159/58/c_k.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.696 ns) + CELL(0.438 ns) 1.134 ns Q~21 2 COMB LCCOMB_X1_Y18_N16 1 " "Info: 2: + IC(0.696 ns) + CELL(0.438 ns) = 1.134 ns; Loc. = LCCOMB_X1_Y18_N16; Fanout = 1; COMB Node = 'Q~21'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.134 ns" { CNT[1] Q~21 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.626 ns) + CELL(2.632 ns) 4.392 ns c_out 3 PIN PIN_R2 0 " "Info: 3: + IC(0.626 ns) + CELL(2.632 ns) = 4.392 ns; Loc. = PIN_R2; Fanout = 0; PIN Node = 'c_out'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.258 ns" { Q~21 c_out } "NODE_NAME" } } { "c_k.vhd" "" { Text "D:/EDA/实验二/06601143-06601159/58/c_k.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.070 ns ( 69.90 % ) " "Info: Total cell delay = 3.070 ns ( 69.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.322 ns ( 30.10 % ) " "Info: Total interconnect delay = 1.322 ns ( 30.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.392 ns" { CNT[1] Q~21 c_out } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.392 ns" { CNT[1] Q~21 c_out } { 0.000ns 0.696ns 0.626ns } { 0.000ns 0.438ns 2.632ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.676 ns" { CLK CLK~clkctrl CNT[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.676 ns" { CLK CLK~combout CLK~clkctrl CNT[1] } { 0.000ns 0.000ns 0.118ns 1.022ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.392 ns" { CNT[1] Q~21 c_out } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.392 ns" { CNT[1] Q~21 c_out } { 0.000ns 0.696ns 0.626ns } { 0.000ns 0.438ns 2.632ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "CLK c_out 4.886 ns Longest " "Info: Longest tpd from source pin \"CLK\" to destination pin \"c_out\" is 4.886 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_P2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 2; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "c_k.vhd" "" { Text "D:/EDA/实验二/06601143-06601159/58/c_k.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.354 ns) + CELL(0.275 ns) 1.628 ns Q~21 2 COMB LCCOMB_X1_Y18_N16 1 " "Info: 2: + IC(0.354 ns) + CELL(0.275 ns) = 1.628 ns; Loc. = LCCOMB_X1_Y18_N16; Fanout = 1; COMB Node = 'Q~21'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.629 ns" { CLK Q~21 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.626 ns) + CELL(2.632 ns) 4.886 ns c_out 3 PIN PIN_R2 0 " "Info: 3: + IC(0.626 ns) + CELL(2.632 ns) = 4.886 ns; Loc. = PIN_R2; Fanout = 0; PIN Node = 'c_out'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.258 ns" { Q~21 c_out } "NODE_NAME" } } { "c_k.vhd" "" { Text "D:/EDA/实验二/06601143-06601159/58/c_k.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.906 ns ( 79.94 % ) " "Info: Total cell delay = 3.906 ns ( 79.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.980 ns ( 20.06 % ) " "Info: Total interconnect delay = 0.980 ns ( 20.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.886 ns" { CLK Q~21 c_out } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.886 ns" { CLK CLK~combout Q~21 c_out } { 0.000ns 0.000ns 0.354ns 0.626ns } { 0.000ns 0.999ns 0.275ns 2.632ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 11 16:43:39 2009 " "Info: Processing ended: Sat Apr 11 16:43:39 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}