📄 low_level_init.c
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/***********************************************************************
* File: low_level_init.c
* Rev: 1.0
* Author: Chun Sing Chu
* Date: March 26 2007
*
* Description:
* This file contains low level initialization of the LPC2478.
*
* Revision History:
* Rev 1.0 March 26 2007
* Initial revision.
*
**********************************************************************/
#include "irq.h"
#include "low_level_init.h"
#include "ex_sdram.h"
/***********************************************************************
*
* Function: delayMs
*
* Purpose: Start the timer delay in micro seconds until elapsed.
*
* Processing:
*
* Parameters: Delay value in micro second
*
* Outputs: None
*
* Returns: None
*
**********************************************************************/
void delayMs(INT32U delayInMs)
{
T1TCR = 0x02; /* reset timer */
T1PR = 0x00; /* set prescaler to zero */
T1MR0 = delayInMs * (18000000 / 1000); /* PCLK is 1/4 CCLK */
T1IR = 0xFF; /* reset all interrrupts */
T1MCR = 0x04; /* stop timer on match */
T1TCR = 0x01; /* start timer */
/* wait until delay time has elapsed */
while (T1TCR & 0x01);
}
/***********************************************************************
*
* Function: configure_pll
*
* Purpose: switching to main OSC from IRC.
*
* Processing:
*
* Parameters: None
*
* Outputs: None
*
* Returns: None
*
**********************************************************************/
void configure_pll(void)
{
INT16U MValue, NValue;
if (PLLSTAT_bit.PLLC)
{
PLLCON_bit.PLLC = 0x0; /* PLL disconnected */
PLLFEED = 0xaa;
PLLFEED = 0x55;
}
PLLCON_bit.PLLE = 0x0; /* PLL disabled */
PLLFEED = 0xaa;
PLLFEED = 0x55;
SCS_bit.OSCEN = 0x1; /* Enable main OSC */
while(!SCS_bit.OSCSTAT); /* Wait until main OSC is usable */
CLKSRCSEL_bit.CLKSRC = 0x1; /* select main OSC, 12MHz, as the PLL clock source */
PLLCFG_bit.MSEL = PLL_MValue;
PLLCFG_bit.NSEL = PLL_NValue;
PLLFEED = 0xaa;
PLLFEED = 0x55;
PLLCON_bit.PLLE = 0x1; /* PLL enabled */
PLLFEED = 0xaa;
PLLFEED = 0x55;
CCLKCFG_bit.CCLKSEL = CCLKDivValue; /* Set clock divider */
while (!PLLSTAT_bit.PLOCK); /* Check lock bit status */
MValue = PLLSTAT_bit.MSEL;
NValue = PLLSTAT_bit.NSEL;
while ((MValue != PLL_MValue) && (NValue != PLL_NValue));
PLLCON_bit.PLLC = 0x1; /* PLL connected */
PLLFEED = 0xaa;
PLLFEED = 0x55;
while (!PLLSTAT_bit.PLLC); /* Check connect bit status */
}
/***********************************************************************
*
* Function: low_level_init
*
* Purpose: initialize the chip.
*
* Processing:
*
* Parameters: None
*
* Outputs: None
*
* Returns: None
*
**********************************************************************/
void low_level_init(void)
{
/* Configure PLL, switch from IRC to Main OSC */
configure_pll();
PCLKSEL0 = 0x00000000; /* PCLK is 1/4 CCLK */
PCLKSEL1 = 0x00000000;
SDRAMInit();
ClearMemory();
PCONP |= 0x00100000; /* Power Control for CLCDC */
/* Set memory accelerater module*/
MAMCR = 0;
MAMTIM = 3; /* Fcclk > 40MHz */
// MAMTIM = 2; /* Fcclk >= 20MHz */
// MAMTIM = 1; /* Fcclk < 20MHz */
MAMCR = 2;
init_vic();
}
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