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📄 sfr_38d2.h

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/***********************************************************************/
/*                                                                     */
/*  FILE        :sfr_38d2.h                                            */
/*  DATE        :Sat, Dec 20, 2008                                     */
/*  DESCRIPTION :sfr file                                              */
/*  CPU GROUP   :38D2                                                  */
/*                                                                     */
/*  This file is generated by Renesas Project Generator (Ver.4.9).     */
/*                                                                     */
/***********************************************************************/
/****************************************************************************
*                                                                           *
*   file name   : intf_38d2.c                                               *
*                                                                           *
*   Version     : 1.00  ( 2006-01-17 ) Initial                              *
*                                                                           *
*   Copyright(C) 2006. Renesas Technology Corp., All rights reserved.       *
*                                                                           *
*****************************************************************************/
/*
  note:
    This data is a freeware that SFR for 38D2 Group is described.
    RENESAS TECHNOLOGY CORPORATION assumes no responsibility for any damage
    that occurred by this data.
*/

#ifndef Chip_38D2
#define Chip_38D2
#endif

#pragma language=extended

/*===================================
 *   Special function registers (SFR)
 *===================================
 */

sfr P0       = 0x00000;      /* Port P0 */
sfr P0D      = 0x00001;      /* Port P0 direction register */
sfr P1       = 0x00002;      /* Port P1 */
sfr P1D      = 0x00003;      /* Port P1 direction register */
sfr P2       = 0x00004;      /* Port P2 */
sfr P2D      = 0x00005;      /* Port P2 direction register */
sfr P3       = 0x00006;      /* Port P3 */
sfr P3D      = 0x00007;      /* Port P3 direction register */
sfr P4       = 0x00008;      /* Port P4 */
sfr P4D      = 0x00009;      /* Port P4 direction register */
sfr P5       = 0x0000a;      /* Port P5 */
sfr P5D      = 0x0000b;      /* Port P5 direction register */
sfr P6       = 0x0000c;      /* Port P6 */
sfr P6D      = 0x0000d;      /* Port P6 direction register */

sfr OSCOUT   = 0x00010;      /* Oscillation output control register */
sfr CPUM2    = 0x00011;      /* CPU mode register 2 */
sfr RRFR     = 0x00012;      /* RRF register */
sfr LM       = 0x00013;      /* LCD mode register */
sfr VLCON    = 0x00014;      /* LCD power control register */
sfr ADCON    = 0x00015;      /* AD control register */
sfr ADL      = 0x00016;      /* AD conversion register (low-order) */
sfr ADH      = 0x00017;      /* AD conversion register (high-order) */
sfr TB1RB1   = 0x00018;      /* Transmit/Receive buffer register 1 */
sfr SIO1STS  = 0x00019;      /* Serial I/O1 status register */
sfr SIO1CON  = 0x0001a;      /* Serial I/O1 control register */
sfr UART1CON = 0x0001b;      /* UART1 control register */
sfr BRG1     = 0x0001c;      /* Baud rate generator 1 */
sfr TB2RB2   = 0x0001d;      /* Transmit/Receive buffer register 2 */
sfr SIO2STS  = 0x0001e;      /* Serial I/O2 status register */
sfr SIO2CON  = 0x0001f;      /* Serial I/O2 control register */

sfr T1       = 0x00020;      /* Timer 1 */
sfr T2       = 0x00021;      /* Timer 2 */
sfr T3       = 0x00022;      /* Timer 3 */
sfr T4       = 0x00023;      /* Timer 4 */
sfr PWM01    = 0x00024;      /* PWM01 register */
sfr T12M     = 0x00025;      /* Timer 12 mode register */
sfr T34M     = 0x00026;      /* Timer 34 mode regiater */
sfr T1234M   = 0x00027;      /* Timer 1234 mode register */
sfr PRE1234  = 0x00028;      /* Timer 1234 frequency division selection register */
sfr WDTCON   = 0x00029;      /* Watchdog timer control register */
sfr TXL      = 0x0002a;      /* Timer X (low-order) */
sfr TXH      = 0x0002b;      /* Timer X (high-order) */
sfr TXEX     = 0x0002c;      /* Timer X (extension) */
sfr TXM      = 0x0002d;      /* Timer X mode register */
sfr TXCON1   = 0x0002e;      /* Timer X control register 1 */
sfr TXCON2   = 0x0002f;      /* Timer X control register 2 */
sfr COMP1L   = 0x00030;      /* Compare register 1 (low-order) */
sfr COMP1H   = 0x00031;      /* Compare register 1 (high-order) */
sfr COMP2L   = 0x00032;      /* Compare register 2 (low-order) */
sfr COMP2H   = 0x00033;      /* Compare register 2 (high-order) */
sfr COMP3L   = 0x00034;      /* Compare register 3 (low-order) */
sfr COMP3H   = 0x00035;      /* Compare register 3 (high-order) */
sfr TYL      = 0x00036;      /* Timer Y (low-order) */
sfr TYH      = 0x00037;      /* Timer Y (high-order) */
sfr TYM      = 0x00038;      /* Timer Y mode regiater */
sfr TYCON    = 0x00039;      /* Timer Y control register */
sfr INTEDGE  = 0x0003a;      /* Interrupt edge selection register */
sfr CPUM     = 0x0003b;      /* CPU mode register */
sfr IREQ1    = 0x0003c;      /* Interrupt request register 1 */
sfr IREQ2    = 0x0003d;      /* Interrupt request register 2 */
sfr ICON1    = 0x0003e;      /* Interrupt control register 1 */
sfr ICON2    = 0x0003f;      /* Interrupt control register 2 */

sfr PULL	 = 0x00ff0;      /* PULL register */
sfr UART2CON = 0x00ff1;      /* UART2 control register */
sfr BRG2     = 0x00ff2;      /* Baud rate generator2 */
sfr CKOUT    = 0x00ff3;      /* Clock output control register */
sfr SEG0     = 0x00ff4;      /* Segment output disable register 0 */
sfr SEG1     = 0x00ff5;      /* Segment output disable register 1 */
sfr SEG2     = 0x00ff6;      /* Segment output disable register 2 */
sfr KIC      = 0x00ff7;      /* Key input control register */
sfr RCA1H    = 0x00ff8;      /* Rom Correction Address Register 1 (High-Order) */
sfr RCA1L    = 0x00ff9;      /* Rom Correction Address Register 1 (Low-Order) */
sfr RCA2H    = 0x00ffa;      /* Rom Correction Address Register 2 (High-Order) */
sfr RCA2L    = 0x00ffb;      /* Rom Correction Address Register 2 (Low-Order) */
sfr RCR      = 0x00ffc;      /* Rom Correction Control Register */

//sfr LRAM[0x004b-0x0040+1] = 0x00040;   /* LCD display RAM */

sfr LRAM0    = 0x00040;
sfr LRAM1    = 0x00041;
sfr LRAM2    = 0x00042;
sfr LRAM3    = 0x00043;
sfr LRAM4    = 0x00044;
sfr LRAM5    = 0x00045;
sfr LRAM6    = 0x00046;
sfr LRAM7    = 0x00047;
sfr LRAM8    = 0x00048;
sfr LRAM9    = 0x00049;
sfr LRAMA    = 0x0004A;
sfr LRAMB    = 0x0004B;

#ifdef __IAR_SYSTEMS_ICC__
/*------------------------------------------------------
  Port P0 register (0000H)
------------------------------------------------------*/
bit P0_0     = P0.0;         /* P0 register bit0 */
bit P0_1     = P0.1;         /* P0 register bit1 */
bit P0_2     = P0.2;         /* P0 register bit2 */
bit P0_3     = P0.3;         /* P0 register bit3 */
bit P0_4     = P0.4;         /* P0 register bit4 */
bit P0_5     = P0.5;         /* P0 register bit5 */
bit P0_6     = P0.6;         /* P0 register bit6 */
bit P0_7     = P0.7;         /* P0 register bit7 */

/*------------------------------------------------------
  Port P1 register (0002H)
------------------------------------------------------*/
bit P1_0     = P1.0;         /* P1 register bit0 */
bit P1_1     = P1.1;         /* P1 register bit1 */
bit P1_2     = P1.2;         /* P1 register bit2 */
bit P1_3     = P1.3;         /* P1 register bit3 */
bit P1_4     = P1.4;         /* P1 register bit4 */
bit P1_5     = P1.5;         /* P1 register bit5 */
bit P1_6     = P1.6;         /* P1 register bit6 */
bit P1_7     = P1.7;         /* P1 register bit7 */

/*------------------------------------------------------
  Port P2 register (0004H)
------------------------------------------------------*/
bit P2_0     = P2.0;         /* P2 register bit0 */
bit P2_1     = P2.1;         /* P2 register bit1 */
bit P2_2     = P2.2;         /* P2 register bit2 */
bit P2_3     = P2.3;         /* P2 register bit3 */
bit P2_4     = P2.4;         /* P2 register bit4 */
bit P2_5     = P2.5;         /* P2 register bit5 */
bit P2_6     = P2.6;         /* P2 register bit6 */
bit P2_7     = P2.7;         /* P2 register bit7 */

/*------------------------------------------------------
  Port P3 register (0006H)
------------------------------------------------------*/
bit P3_0     = P3.0;         /* P3 register bit0 */
bit P3_1     = P3.1;         /* P3 register bit1 */
bit P3_2     = P3.2;         /* P3 register bit2 */
bit P3_3     = P3.3;         /* P3 register bit3 */
bit P3_4     = P3.4;         /* P3 register bit4 */
bit P3_5     = P3.5;         /* P3 register bit5 */
bit P3_6     = P3.6;         /* P3 register bit6 */
bit P3_7     = P3.7;         /* P3 register bit7 */

/*------------------------------------------------------
  Port P4 register (0008H)
------------------------------------------------------*/
bit P4_0     = P4.0;         /* P4 register bit0 */
bit P4_1     = P4.1;         /* P4 register bit1 */
bit P4_2     = P4.2;         /* P4 register bit2 */
bit P4_3     = P4.3;         /* P4 register bit3 */
bit P4_4     = P4.4;         /* P4 register bit4 */
bit P4_5     = P4.5;         /* P4 register bit5 */
bit P4_6     = P4.6;         /* P4 register bit6 */
bit P4_7     = P4.7;         /* P4 register bit7 */

/*------------------------------------------------------
  Port P5 register (000AH)
------------------------------------------------------*/
bit P5_0     = P5.0;         /* P5 register bit0 */
bit P5_1     = P5.1;         /* P5 register bit1 */
bit P5_2     = P5.2;         /* P5 register bit2 */
bit P5_3     = P5.3;         /* P5 register bit3 */
bit P5_4     = P5.4;         /* P5 register bit4 */
bit P5_5     = P5.5;         /* P5 register bit5 */
bit P5_6     = P5.6;         /* P5 register bit6 */
bit P5_7     = P5.7;         /* P5 register bit7 */

/*------------------------------------------------------
  Port P6 register (000CH)
------------------------------------------------------*/
bit P6_0     = P6.0;         /* P6 register bit0 */
bit P6_1     = P6.1;         /* P6 register bit1 */
bit P6_2     = P6.2;         /* P6 register bit2 */
#endif

/*------------------------------------------------------
  Oscillation Output Control Register (0010H)
------------------------------------------------------*/
bit OOC0		= OSCOUT.0;		/* Oscillation Output Control Bits(0,1) */
bit OOC1		= OSCOUT.1;		/*  */

/*------------------------------------------------------
  CPU Mode2 Register (0011H)
------------------------------------------------------*/
bit CM8			= CPUM2.0;		/* On-chip Oscillator Stop Bit */

/*------------------------------------------------------
  RRF Register (0012H)
------------------------------------------------------*/
bit RRFR0		= RRFR.0;		/* DB4 Data Storage */
bit RRFR1		= RRFR.1;		/* DB5 Data Storage */
bit RRFR2		= RRFR.2;		/* DB6 Data Storage */
bit RRFR3		= RRFR.3;		/* DB7 Data Storage */
bit RRFR4		= RRFR.4;		/* DB0 Data Storage */
bit RRFR5		= RRFR.5;		/* DB1 Data Storage */
bit RRFR6		= RRFR.6;		/* DB2 Data Storage */
bit RRFR7		= RRFR.7;		/* DB3 Data Storage */
 
/*------------------------------------------------------
  LCD Mode Register (0013H)
------------------------------------------------------*/
bit DRS0		= LM.0;			/* Duty Ratio Selection Bits (0,1) */
bit DRS1		= LM.1;			/*  */
bit LMBC		= LM.2;			/* Bias Control Bit */
bit LME			= LM.3;			/* LCD Enable Bit */
bit LMDTS		= LM.4;			/* LCD Drive Timing Selection Bit */
bit LMDD0		= LM.5;			/* LCD Circuit Divider Division Ratio Selection Bits (5,6) */
bit LMDD1		= LM.6;			/*  */
bit LCDCK		= LM.7;			/* LCDCK Count Source Selection Bit */

/*------------------------------------------------------
  LCD Power Control Register (0014H)
------------------------------------------------------*/
bit LCDRON		= VLCON.0;		/* Dividing Resistor for LCD Power Control Bit */
bit RSEL0		= VLCON.1;		/* Dividing Resistor for LCD Power Selection Bits (1,2) */
bit RSEL1		= VLCON.2;		/*  */
bit VLSEL		= VLCON.5;		/* VL Pin Input Selection Bit */
bit VL3C		= VLCON.6;		/* VL3 Connection Bit */

/*------------------------------------------------------
  AD Control Register (0015H)

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