📄 mac_cc2430.h
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/*******************************************************************************************************
* *
* ********** *
* ************ *
* *** *** *
* *** +++ *** *
* *** + + *** *
* *** + CHIPCON CC2430 INTEGRATED 802.15.4 MAC AND PHY *
* *** + + *** MAC-CC2430.H *
* *** +++ *** *
* *** *** *
* ************ *
* ********** *
* *
*******************************************************************************************************
* CONFIDENTIAL *
* The use of this file is restricted by the signed MAC software license agreement. *
* *
* Copyright Chipcon AS, 2005 *
*******************************************************************************************************/
extern DMA_CHANNEL_CONFIGURATION pDma1234Configs[4];
#define READ_RFR16(reg) ((((WORD) ##reg## H) << 8) + ##reg## L)
#define WRITE_RFR16(reg, value) do { ##reg## H = HIBYTE(value); ##reg## L = LOBYTE(value); } while (0)
#define SET_FIFOP_THRESHOLD(t) (IOCFG0 = (t) - 1)
#define RESET_FIFOP_THRESHOLD() SET_FIFOP_THRESHOLD(4)
//#define RSSI_2_ED(rssi) ((rssi) < RSSI_OFFSET ? 0 : ((rssi) - (RSSI_OFFSET)))
#define CC2430_TX_ACTIVE_BM BM(3)
/******************************************************************************
* Constants *
******************************************************************************/
#define AES_START_COMMAND 0x01
#define AES_COMMAND_POSITION 0x01
#define AES_MODE_POSITION 0x04
#define AES_CTR_FLAGS_FIELD 0x82
#define AES_WAIT_TIME 0xff
#define SIXTEEN_BYTES_BLOCK 16
#define RESULT_128 16
#define RESULT_64 8
#define RESULT_32 4
#define B0_M128_L2 0x69
#define B0_M64_L2 0x59
#define B0_M32_L2 0x51
#define A0_L2 0x01
#define REMAINING_FOUR_BITS 0x0f
#define MAX_IN_AES 240
#define USE_DMA_FOR_MEMCPY_THRESHOLD 0x10
#define DMA_TO_AES_CHANNEL_NO 1
#define DMA_FROM_AES_CHANNEL_NO 2
#define DMA_CHANNEL_NO_3 3
#define DMA_RFRX_CHANNEL 4
#define DMA_TO_AES_INTERRUPT_MASK 0x2
#define DMA_FROM_AES_INTERRUPT_MASK 0x4
#define DMA_CHANNEL_NO_3_INTERRUPT_MASK 0x8
#define DMA_RFRX_CHANNEL_BM 0x10
#define DMA_TO_AES_START 0x2
#define DMA_FROM_AES_START 0x4
#define DMA_CHANNEL_NO_3_START 0x8
#define DMA_RF_START 0x10
#define DMA_TO_AES_STOP 0x82
#define DMA_FROM_AES_STOP 0x84
#define DMA_CHANNEL_NO_3_STOP 0x88
#define DMA_RF_STOP 0x90
#define MSB_DMA_SRC_ADDR_OFFSET 0
#define LSB_DMA_SRC_ADDR_OFFSET 1
#define MSB_DMA_DST_ADDR_OFFSET 2
#define LSB_DMA_DST_ADDR_OFFSET 3
#define DMA_TRANSFER_AND_LEN_MSB_OFFSET 4
#define DMA_LEN_LSB_OFFSET 5
#define DMA_TRANSFER_AND_TRIGGER_OFFSET 6
#define DMA_MISC_SETUP_OFFSET 7
#define USE_LEN 0x0
#define USE_FIRST_BYTE_AS_LEN 0x20
#define BYTE_TRANSFER 0x0
#define WORD_TRANSFER 0x80
#define TRANSFER_MODE_SINGLE 0x0
#define TRANSFER_MODE_BLOCK 0x20
#define TRANSFER_MODE_REPEATED_SINGLE 0x40
#define TRANSFER_MODE_REPEATED_BLOCK 0x60
#define DMA_RF_TRIGGER 0x13
#define DMA_FROM_AES_TRIGGER 0x1E
#define DMA_TO_AES_TRIGGER 0x1D
#define SRC_INC_NONE 0x0
#define SRC_INC_ONE_BYTE 0x40
#define DST_INC_NONE 0x0
#define DST_INC_ONE_BYTE 0x10
#define DMA_IRQ_ENABLE 0x08
#define DMA_IRQ_DISABLE 0x00
#define DMA_7_BIT_TRANSFER_COUNT 0x04
#define DMA_8_BIT_TRANSFER_COUNT 0x0
#define DMA_PRIORITY_LOW 0x0
#define DMA_PRIORITY_MEDIUM 0x01
#define DMA_PRIORITY_HIGH 0x02
#define DMA_PRIORITY_HIGHEST 0x03
#define MCU_AES_INTERRUPT_BM 0x01
#define MCU_DMA_INTERRUPT_BM 0x01
#define MCU_RFIF_INTERRUPT_BM 0x01
#define MCU_RFERR_INTERRUPT_BM 0x01
#define MCU_TIMER2_INTERRUPT_BM 0x04
#define MCU_ENABLE_ALL_INTERRUPTS_BM 0x80
#define MCU_AES_INTERRUPT_VECTOR_NO ENC_int
#define MCU_DMA_INTERRUPT_VECTOR_NO DMA_int
#define MCU_RFERR_INTERRUPT_VECTOR_NO RFERR_int
#define MCU_RFIF_INTERRUPT_VECTOR_NO RF_int
#define MCU_TIMER2_INTERRUPT_VECTOR_NO T2_int
#define RFIF_CSP_MANINT_BM 0x01
#define RFIF_CSP_STOP_BM 0x02
#define RFIF_CSP_WAIT_BM 0x04
#define RFIF_CCA_BM 0x08
#define RFIF_SFD_BM 0x10
#define RFIF_FIFOP_BM 0x20
#define RFIF_TXDONE_BM 0x40
#define RFIF_RREG_PD_BM 0x80
#define RF_CLEAR_INTERRUPT_MASK 0x0
#define RF_CLEAR_ALL_INTERRUPTS 0x0
#define RF_SET_INTERRUPT_MASK 0x62
#define RF_STROBE_CSP_MCU_ON 0x00
#define RF_STROBE_CSP_MCU_OFF 0x01
#define CSP_TIMEOUT_RUN_FOREVER 0xFF
#define CSP_TIMEOUT_STOP 0x00
#define TIMER2_COMPARE_EVENT_INTERRUPT_BM 0x80
#define TIMER2_PERIOD_EVENT_INTERRUPT_BM 0x40
#define TIMER2_OVERFLOW_COMPARE_INTERRUPT_BM 0x20
#define TIMER2_RUN_BM 0x01
#define TIMER2_BACKOFF_SLOT_COUNTER_VALUE 0x2800
#define TIMER2_BACKOFF_SLOT_DELTA_COMPARE_VALUE TIMER2_BACKOFF_SLOT_COUNTER_VALUE - 0x400
#define TIMER2_INITIAL_OVERFLOW_PERIOD_VALUE 0x06
#define TIMER2_INTERRUPT_MASK 0xC0
#define START_TIMER2 0x01
#define TRANSMITTER_DELAY 0x45
#define INCREMENT_BOS_COUNTER_DUE_TO_STRETCHING_BACKOFF_SLOT 0x01
/***********************************************************************************************
* CC2430 RF register constants *
***********************************************************************************************/
#define RESET_RF_CHIP_ON 0x80
#define RESET_RF_CHIP_OFF 0x0
#define VREG_POWER_UP 0x04
#define VREG_POWER_DOWN 0x04
#define RF_RX_OVERFLOW 0x11
#define RF_TX_UNDERFLOW 0x38
#define ACCEPT_ACKPKT 0x01
#define ABORT_RX_ON_SRXON 0x20
#define RFSTATUS_TX_ACTIVE_BM 0x10
#define RFSTATUS_SFD_BM 0x02
#define SFD_IS_ACTIVE() (RFSTATUS & 0x02)
#define FSMTC1_ABORTRX_ON_SRXON_BM 0x20
#define FSMTC1_RX_INTERRUPTED_BM 0x10
#define FSMTC1_AUTO_TX2RX_OFF_BM 0x08
#define FSMTC1_RX2RX_TIME_OFF_BM 0x04
#define FSMTC1_PENDING_OR_BM 0x02
#define FSMTC1_ACCEPT_ACKPKT_BM 0x01
// Command strobes
#define CC2430_WAITX 0xBB
#define CC2430_RANDXY 0xBC
//CFR
/*
#define ISSNOP() (RFST = 0xE0)
#define ISRXON() (RFST = 0xE2)
#define ISTXON() (RFST = 0xE3)
#define ISTXONCCA() (RFST = 0xE4)
#define ISRFOFF() (RFST = 0xE5)
#define ISFLUSHRX() (RFST = 0xE6)
#define ISFLUSHTX() (RFST = 0xE7)
#define ISACK() (RFST = 0xE8)
#define ISACKPEND() (RFST = 0xE9)
#define ISTXCALN() (RFST = 0xE1)
#define ISSTART() (RFST = 0xFE)
#define ISSTOP() (RFST = 0xFF)
*/
#define CSP_INSTR_SNOP 0xC0
#define CSP_INSTR_WAITX 0xBB
#define CSP_PROGRAM_TERMINATOR 0xC0
#define CSP_INDICATE_RX_ON(bool) (CSPCTRL = bool)
#define MAX_STROBE_CODE_LENGTH 24
#define ENABLE_FIFOP_INT_BIT() SET_RFIM(RFIM | RFIF_FIFOP_BM)
#define DISABLE_FIFOP_INT_BIT() SET_RFIM(RFIM & ~RFIF_FIFOP_BM)
#define CLEAR_FIFOP_INT_BIT() SET_RFIF(~RFIF_FIFOP_BM)
#define CLEAR_RFIF_INT() do { S1CON = 0x00; SET_RFIM(RFIM); } while (0)
#define ENABLE_RFIF_INT() (IEN2 |= 0x01)
#define DISABLE_RFIF_INT() (IEN2 &= ~0x01)
#define CLEAR_DMA_INT() (DMAIF = 0)
#define ENABLE_DMA_INT() (DMAIE = 1)
#define DISABLE_DMA_INT() (DMAIE = 0)
#define PAN_COORDINATOR_BM 0x1000
#define MDMCTRL0_NO_PAN_COORDINATOR 0x0AE2
#define MDMCTRL0_PAN_COORDINATOR 0x1AE2
#define ENABLE_AUTOACK() (MDMCTRL0L |= 0x10)
#define DISABLE_AUTOACK() (MDMCTRL0L &= ~0x10)
#define AUTOACK_WITH_PENDING_BIT() (FSMTC1 |= 0x02)
#define AUTOACK_WITHOUT_PENDING_BIT() (FSMTC1 &= ~0x02)
//====================================================//
// This value is changed to support locatione engine
// the original value in Chicon Mac is -49
#define RSSI_OFFSET_VALUE -60
//====================================================//
#define RSSI_2_ED(rssi) ((rssi) < RSSI_OFFSET_VALUE ? 0 : ((rssi) - (RSSI_OFFSET_VALUE)))
#define ED_2_LQI(ed) (((ed) > 63 ? 255 : ((ed) << 2)))
//CFR
/*
#define DMA_ARM_CHANNEL(c) \
do { \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
DMAARM = BM(c); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
asm("NOP"); \
} while (0)
#define DMA_START_CHANNEL(c) (DMAREQ = BM(c))
#define DMA_ABORT_CHANNEL(c) (DMAARM = 0x80 | BM(c))
*/
//-------------------------------------------------------------------------------------------------------
// Transmit power values from 0dBm to -25dBm
//-------------------------------------------------------------------------------------------------------
#define CC2430_0DBM 0xA0FF
#define CC2430_N1DBM 0xA0FB
#define CC2430_N3DBM 0xA0F7
#define CC2430_N5DBM 0xA0F3
#define CC2430_N7DBM 0xA0EF
#define CC2430_N10DBM 0xA0EB
#define CC2430_N15DBM 0xA0E7
#define CC2430_N25DBM 0xA0E3
//-------------------------------------------------------------------------------------------------------
// CC2430 power control
//-------------------------------------------------------------------------------------------------------
#define CC2430_PM1 0x01
#define CC2430_PM2 0x02
#define CC2430_PM3 0x03
/******************************************************************************
* Prototypes *
******************************************************************************/
#define DISABLE_GLOBAL_INT() (EA = FALSE)
#define ENABLE_GLOBAL_INT() (EA = TRUE)
void DisableAesInterrupt (void);
ROOT void DisableRfInterrupts (void);
void EnableAesInterrupt (void);
ROOT void EnableRfInterrupts (void);
ROOT void FetchDmaChannelConfiguration (BYTE dmaChannelNo,
DMA_CHANNEL_CONFIGURATION **dmaChannelConfiguration);
ROOT void InitializeDma(void);
ROOT void InitializeRfInterrupts (void);
ROOT void StartDma (BYTE dmaChannelNo);
ROOT void WriteRfInterruptMaskRegister (BYTE interruptMask);
ROOT void WriteRfInterruptRegister (BYTE interruptValue);
ROOT void halMacWait(UINT16 timeout);
ROOT void SET_RFIF(BYTE value);
ROOT void SET_RFIM(BYTE value);
void halReadRxFifo(BYTE *pData, UINT8 count);
void halDiscardRxFifo(UINT8 count);
void halWriteTxFifo(BYTE *pData, UINT8 count);
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