📄 mac_cc2430.lst
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\ 000054 E4 CLR A
\ 000055 90.... MOV DPTR,#(pDma1234Configs + 12)
\ 000058 F0 MOVX @DPTR,A
\ 000059 741E MOV A,#0x1e
\ 00005B 90.... MOV DPTR,#(pDma1234Configs + 14)
\ 00005E F0 MOVX @DPTR,A
\ 00005F 7412 MOV A,#0x12
\ 000061 90.... MOV DPTR,#(pDma1234Configs + 15)
\ 000064 F0 MOVX @DPTR,A
54 EnableMcuDmaInterrupt ();
\ 000065 C2C0 CLR 0xc0.0
\ 000067 D2B8 SETB 0xb8.0
55
56 }
\ 000069 REQUIRE ?Subroutine0
\ 000069 ; // Fall through to label ?Subroutine0
\ In segment NEAR_CODE, align 1, keep-with-next
\ ?Subroutine0:
\ 000000 D083 POP DPH
\ 000002 D082 POP DPL
\ 000004 22 RET
57
58 //-------------------------------------------------------------------------------------------------------
59 //
60 //-------------------------------------------------------------------------------------------------------
\ In segment NEAR_CODE, align 1, keep-with-next
61 ROOT void FetchDmaChannelConfiguration (BYTE dmaChannelNo,
\ FetchDmaChannelConfiguration:
62 DMA_CHANNEL_CONFIGURATION **dmaChannelConfiguration)
63 {
\ 000000 74F7 MOV A,#-0x9
\ 000002 12.... LCALL ?FUNC_ENTER_XDATA
\ 000005 ; Saved register size: 9
\ 000005 ; Auto size: 0
64 *dmaChannelConfiguration = &pDma1234Configs[dmaChannelNo - 1];
\ 000005 89.. MOV ?V0 + 0,R1
\ 000007 75..00 MOV ?V0 + 1,#0x0
\ 00000A 7403 MOV A,#0x3
\ 00000C 78.. MOV R0,#?V0 + 0
\ 00000E 12.... LCALL ?S_SHL
\ 000011 E5.. MOV A,?V0 + 0
\ 000013 24.. ADD A,#((pDma1234Configs + 248) & 0xff)
\ 000015 F8 MOV R0,A
\ 000016 E5.. MOV A,?V0 + 1
\ 000018 34.. ADDC A,#(((pDma1234Configs - 8) >> 8) & 0xff)
\ 00001A F9 MOV R1,A
\ 00001B 8A82 MOV DPL,R2
\ 00001D 8B83 MOV DPH,R3
\ 00001F E8 MOV A,R0
\ 000020 F0 MOVX @DPTR,A
\ 000021 A3 INC DPTR
\ 000022 E9 MOV A,R1
\ 000023 F0 MOVX @DPTR,A
65 }
\ 000024 7F02 MOV R7,#0x2
\ 000026 02.... LJMP ?FUNC_LEAVE_XDATA
66
67
68 //-------------------------------------------------------------------------------------------------------
69 //
70 //-------------------------------------------------------------------------------------------------------
\ In segment NEAR_CODE, align 1, keep-with-next
71 ROOT void StartDma (BYTE dmaChannelNo)
\ StartDma:
72 {
\ 000000 C082 PUSH DPL
\ 000002 C083 PUSH DPH
\ 000004 ; Saved register size: 2
\ 000004 ; Auto size: 0
73 switch (dmaChannelNo)
\ 000004 E9 MOV A,R1
\ 000005 12.... LCALL ?UC_SWITCH_DENSE
\ `?<Jumptable for StartDma>_0`:
\ 000008 01 DB 1
\ 000009 03 DB 3
\ 00000A .... DW ??StartDma_0
\ 00000C .... DW ??StartDma_1
\ 00000E .... DW ??StartDma_2
\ 000010 .... DW ??StartDma_3
\ 000012 .... DW ??StartDma_4
74 {
75
76 case DMA_TO_AES_CHANNEL_NO:
77 DMAIRQ &= ~DMA_TO_AES_INTERRUPT_MASK;
\ ??StartDma_1:
\ 000014 53D1FD ANL 0xd1,#0xfd
78 DMAARM = DMA_TO_AES_START;
\ 000017 75D602 MOV 0xd6,#0x2
\ 00001A 801C SJMP ??StartDma_0
79 break;
80
81 case DMA_FROM_AES_CHANNEL_NO:
82 DMAIRQ &= ~DMA_FROM_AES_INTERRUPT_MASK;
\ ??StartDma_2:
\ 00001C 53D1FB ANL 0xd1,#0xfb
83 DMAARM = DMA_FROM_AES_START;
\ 00001F 75D604 MOV 0xd6,#0x4
\ 000022 8014 SJMP ??StartDma_0
84 break;
85
86 case DMA_CHANNEL_NO_3:
87 DMAIRQ &= ~DMA_CHANNEL_NO_3_INTERRUPT_MASK;
\ ??StartDma_3:
\ 000024 53D1F7 ANL 0xd1,#0xf7
88 DMAARM = DMA_CHANNEL_NO_3_START;
\ 000027 75D608 MOV 0xd6,#0x8
89 DMAREQ = DMA_CHANNEL_NO_3_START;
\ 00002A 75D708 MOV 0xd7,#0x8
\ 00002D 8009 SJMP ??StartDma_0
90 break;
91
92 case DMA_RFRX_CHANNEL:
93 DMAIRQ &= ~DMA_RFRX_CHANNEL_BM;
\ ??StartDma_4:
\ 00002F 53D1EF ANL 0xd1,#0xef
94 DMAARM = DMA_RF_START;
\ 000032 75D610 MOV 0xd6,#0x10
95 DMAREQ = DMA_RF_START;
\ 000035 75D710 MOV 0xd7,#0x10
96 break;
97
98 }
99 }
\ ??StartDma_0:
\ 000038 80.. SJMP ?Subroutine0
100
101 //-------------------------------------------------------------------------------------------------------
102 //
103 //-------------------------------------------------------------------------------------------------------
104 static ROOT void EnableMcuDmaInterrupt (void)
105 {
106 DMAIF /*IEX7*/ = FALSE;
107 DMAIE /*EX7*/ = TRUE;
108 }
109
110 //-------------------------------------------------------------------------------------------------------
111 //
112 //-------------------------------------------------------------------------------------------------------
113 static ROOT void InitializeDmaRf (void)
114 {
115 pDma1234Configs[DMA_RFRX_CHANNEL - 1].srcMsb = HIBYTE(&X_RFD);
116 pDma1234Configs[DMA_RFRX_CHANNEL - 1].srcLsb = LOBYTE(&X_RFD);
117 pDma1234Configs[DMA_RFRX_CHANNEL - 1].lenMsb = 0x00;
118 pDma1234Configs[DMA_RFRX_CHANNEL - 1].wsizeTmodeTrigger = BYTE_TRANSFER | TRANSFER_MODE_SINGLE | DMA_RF_TRIGGER;
119 pDma1234Configs[DMA_RFRX_CHANNEL - 1].incIrqM8Pri = SRC_INC_NONE | DST_INC_ONE_BYTE | DMA_IRQ_ENABLE | DMA_7_BIT_TRANSFER_COUNT | DMA_PRIORITY_LOW;
120 }
121
122 //-------------------------------------------------------------------------------------------------------
123 //
124 //-------------------------------------------------------------------------------------------------------
125 static ROOT void InitializeDmaAes (void)
126 {
127 DMA_CHANNEL_CONFIGURATION *dmaChannelConfiguration;
128
129 FetchDmaChannelConfiguration (DMA_TO_AES_CHANNEL_NO, &dmaChannelConfiguration);
130
131 dmaChannelConfiguration->destMsb = (BYTE)(((WORD) &X_ENCDI) >> 8);
132 dmaChannelConfiguration->destLsb = (BYTE)( (WORD) &X_ENCDI);
133 dmaChannelConfiguration->lenMsb = USE_LEN;
134 dmaChannelConfiguration->wsizeTmodeTrigger = BYTE_TRANSFER +
135 TRANSFER_MODE_SINGLE +
136 DMA_TO_AES_TRIGGER;
137 dmaChannelConfiguration->incIrqM8Pri = SRC_INC_ONE_BYTE +
138 DST_INC_NONE +
139 DMA_IRQ_DISABLE +
140 DMA_8_BIT_TRANSFER_COUNT +
141 DMA_PRIORITY_HIGH;
142
143 FetchDmaChannelConfiguration (DMA_FROM_AES_CHANNEL_NO, &dmaChannelConfiguration);
144
145 dmaChannelConfiguration->srcMsb = (BYTE)(((WORD) &X_ENCDO) >> 8);
146 dmaChannelConfiguration->srcLsb = (BYTE)( (WORD) &X_ENCDO);
147 dmaChannelConfiguration->lenMsb = USE_LEN;
148 dmaChannelConfiguration->wsizeTmodeTrigger = BYTE_TRANSFER +
149 TRANSFER_MODE_SINGLE +
150 DMA_FROM_AES_TRIGGER;
151 dmaChannelConfiguration->incIrqM8Pri = SRC_INC_NONE +
152 DST_INC_ONE_BYTE +
153 DMA_IRQ_DISABLE +
154 DMA_8_BIT_TRANSFER_COUNT +
155 DMA_PRIORITY_HIGH;
156
157 }
158
159 //-------------------------------------------------------------------------------------------------------
160 //
161 // RF routines
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