📄 mac_support.s51
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CFI CFA_SP SP+-3
PUSH DPH
CFI DPH0 Frame(CFA_SP, 4)
CFI CFA_SP SP+-4
; Saved register size: 2
; Auto size: 0
// 171 UINT8 rfrFsmstate = FSMSTATE;
MOV DPTR,#-0x20c7
MOVX A,@DPTR
MOV R2,A
// 172 return (((rfrFsmstate >= 7) && (rfrFsmstate <= 13)) || // RX
// 173 ((rfrFsmstate >= 51) && (rfrFsmstate <= 54)) || // TX ack
// 174 ((rfrFsmstate >= 36) && (rfrFsmstate <= 39))); // TX
CLR C
SUBB A,#0x7
JC ??msupIsSfdActive_0
MOV A,R2
CLR C
SUBB A,#0xe
JC ??msupIsSfdActive_1
??msupIsSfdActive_0:
MOV A,R2
CLR C
SUBB A,#0x33
MOV A,R2
JC ??msupIsSfdActive_2
CLR C
SUBB A,#0x37
JC ??msupIsSfdActive_1
??msupIsSfdActive_3:
MOV R1,#0x0
??msupIsSfdActive_4:
SJMP ?Subroutine1
??msupIsSfdActive_2:
CLR C
SUBB A,#0x24
JC ??msupIsSfdActive_3
MOV A,R2
CLR C
SUBB A,#0x28
JNC ??msupIsSfdActive_3
??msupIsSfdActive_1:
MOV R1,#0x1
SJMP ??msupIsSfdActive_4
CFI EndBlock cfiBlock5
// 175 }
// 176
RSEG NEAR_CODE:CODE:NOROOT(0)
// 177 ROOT BOOL msupIsTxActive(void) {
msupIsTxActive:
CFI Block cfiBlock6 Using cfiCommon1
CFI Function msupIsTxActive
PUSH DPL
CFI DPL0 Frame(CFA_SP, 3)
CFI CFA_SP SP+-3
PUSH DPH
CFI DPH0 Frame(CFA_SP, 4)
CFI CFA_SP SP+-4
; Saved register size: 2
; Auto size: 0
// 178 if (FSMSTATE & 0x30) {
MOV DPTR,#-0x20c7
MOVX A,@DPTR
ANL A,#0x30
JZ ??msupIsTxActive_0
// 179 return TRUE;
MOV R1,#0x1
SJMP ??msupIsTxActive_1
// 180 } else {
// 181 return FALSE;
??msupIsTxActive_0:
MOV R1,#0x0
??msupIsTxActive_1:
SJMP ?Subroutine1
CFI EndBlock cfiBlock6
// 182 }
// 183 }
// 184
RSEG NEAR_CODE:CODE:NOROOT(0)
// 185 ROOT BOOL msupIsCspInCriticalSection(void) {
msupIsCspInCriticalSection:
CFI Block cfiBlock7 Using cfiCommon1
CFI Function msupIsCspInCriticalSection
PUSH DPL
CFI DPL0 Frame(CFA_SP, 3)
CFI CFA_SP SP+-3
PUSH DPH
CFI DPH0 Frame(CFA_SP, 4)
CFI CFA_SP SP+-4
; Saved register size: 2
; Auto size: 0
// 186 switch (RFST) {
MOV A,0xe1
LCALL ?UC_SWITCH_SPARSE
`?<Jumptable for msupIsCspInCriticalSection>_0`:
DB 0
DB 2
DB 187
DW ??msupIsCspInCriticalSection_0
DB 192
DW ??msupIsCspInCriticalSection_0
DW ??msupIsCspInCriticalSection_1
// 187 case CSP_INSTR_SNOP:
// 188 case CSP_INSTR_WAITX:
// 189 return FALSE;
??msupIsCspInCriticalSection_0:
MOV R1,#0x0
SJMP ??msupIsCspInCriticalSection_2
// 190 default:
// 191 return TRUE;
??msupIsCspInCriticalSection_1:
MOV R1,#0x1
??msupIsCspInCriticalSection_2:
SJMP ?Subroutine1
CFI EndBlock cfiBlock7
// 192 }
// 193 }
// 194
// 195
// 196
// 197 //-------------------------------------------------------------------------------------------------------
// 198 // void msupInitRandomGenerator(void)
// 199 //
// 200 // DESCRIPTION:
// 201 // Uses the IEEE extended address to seed the hardware random generator
// 202 //-------------------------------------------------------------------------------------------------------
RSEG NEAR_CODE:CODE:NOROOT(0)
// 203 ROOT void msupInitRandomGenerator(BYTE *pExtendedAddr) {
msupInitRandomGenerator:
CFI Block cfiBlock8 Using cfiCommon1
CFI Function msupInitRandomGenerator
PUSH DPL
CFI DPL0 Frame(CFA_SP, 3)
CFI CFA_SP SP+-3
PUSH DPH
CFI DPH0 Frame(CFA_SP, 4)
CFI CFA_SP SP+-4
; Saved register size: 2
; Auto size: 0
// 204 UINT8 n;
// 205
// 206 // Initialize the LFSR
// 207 RNDL = 0xFF;
MOV 0xbc,#-0x1
// 208 RNDL = 0xFF;
MOV 0xbc,#-0x1
// 209
// 210 // Make it "random"
// 211 for (n = 0; n < sizeof(ADDRESS); n++) {
MOV R4,#0x8
// 212 RNDH = pExtendedAddr[n];
??msupInitRandomGenerator_0:
MOV DPL,R2
MOV DPH,R3
MOVX A,@DPTR
MOV 0xbd,A
// 213 }
INC DPTR
MOV R2,DPL
MOV R3,DPH
DEC R4
MOV A,R4
JNZ ??msupInitRandomGenerator_0
CFI EndBlock cfiBlock8
// 214
// 215 } // msupInitRandomGenerator
REQUIRE ?Subroutine1
; // Fall through to label ?Subroutine1
RSEG NEAR_CODE:CODE:NOROOT(0)
?Subroutine1:
CFI Block cfiBlock9 Using cfiCommon1
CFI NoFunction
CFI CFA_SP SP+-4
CFI DPL0 Frame(CFA_SP, 3)
CFI DPH0 Frame(CFA_SP, 4)
POP DPH
CFI CFA_SP SP+-3
CFI DPH0 SameValue
POP DPL
CFI CFA_SP SP+-2
CFI DPL0 SameValue
RET
CFI EndBlock cfiBlock9
// 216
// 217
// 218
// 219 //-------------------------------------------------------------------------------------------------------
// 220 // BYTE msupGetRandomByte(void)
// 221 //
// 222 // DESCRIPTION:
// 223 // Generates a single pseudo-random byte from the LFSR in the hardware random generator
// 224 // Use msupInitRandomGenerator() to seed the LFSR
// 225 //
// 226 // RETURN VALUE:
// 227 // BYTE
// 228 // Random value
// 229 //-------------------------------------------------------------------------------------------------------
RSEG NEAR_CODE:CODE:NOROOT(0)
// 230 ROOT BYTE msupGetRandomByte(void) {
msupGetRandomByte:
CFI Block cfiBlock10 Using cfiCommon1
CFI Function msupGetRandomByte
; Saved register size: 0
; Auto size: 0
// 231 ADCCON1 &= ~0x0C;
ANL 0xb4,#0xf3
MOV A,0xb4
// 232 ADCCON1 |= 0x04;
ORL 0xb4,#0x4
// 233 return RNDH;
MOV R1,0xbd
RET
CFI EndBlock cfiBlock10
// 234 } // msupGetRandomByte
// 235
// 236
// 237
// 238
// 239 /*******************************************************************************************************
// 240 *******************************************************************************************************
// 241 ************************** RF CHANNEL SETTINGS **************************
// 242 *******************************************************************************************************
// 243 *******************************************************************************************************/
// 244
// 245 //-------------------------------------------------------------------------------------------------------
// 246 // BOOL msupChannelValid(UINT8 logicalChannel)
// 247 //
// 248 // DESCRIPTION:
// 249 // Support function for verifying that the logicalChannel is within the valid range for the 2.4 GHz
// 250 // channels supported by CC2430, which are channels 11 (2405 MHz) through 26 (2480 MHz).
// 251 //
// 252 // PARAMETERS:
// 253 // UINT8 logicalChannel
// 254 // The channel number
// 255 //
// 256 // RETURN VALUE:
// 257 // BOOL
// 258 // TRUE for channels >= 11 and <= 26, otherwise FALSE
// 259 //-------------------------------------------------------------------------------------------------------
RSEG NEAR_CODE:CODE:NOROOT(0)
// 260 ROOT BOOL msupChannelValid(UINT8 logicalChannel) {
msupChannelValid:
CFI Block cfiBlock11 Using cfiCommon1
CFI Function msupChannelValid
; Saved register size: 0
; Auto size: 0
// 261 return ((BOOL)((logicalChannel >= 11) && (logicalChannel <= 26)));
MOV A,R1
CLR C
SUBB A,#0xb
JC ??msupChannelValid_0
MOV A,R1
CLR C
SUBB A,#0x1b
JNC ??msupChannelValid_0
MOV R1,#0x1
RET
??msupChannelValid_0:
MOV R1,#0x0
RET
CFI EndBlock cfiBlock11
// 262 } // msupChannelValid
// 263
// 264
// 265
// 266
// 267 //-------------------------------------------------------------------------------------------------------
// 268 // void msupSetChannel(UINT8 logicalChannel, BOOL changePib)
// 269 //
// 270 // DESCRIPTION:
// 271 // Changes the radio channel if necessary. The function calculates the new value for the FSCTRL
// 272 // register, and compares it to the current value. When different, the frequency will be changed.
// 273 // The function will clean up the RX engine if we're interrupting a reception. When finished, it
// 274 // will restore the previous RX state.
// 275 //
// 276 // PARAMETERS:
// 277 // UINT8 logicalChannel
// 278 // The channel number, 11 - 26
// 279 // BOOL changePib
// 280 // Set ppib.phyCurrentChannel = logicalChannel?
// 281 //-------------------------------------------------------------------------------------------------------
RSEG NEAR_CODE:CODE:NOROOT(0)
// 282 ROOT void msupSetChannel(UINT8 logicalChannel, BOOL changePib) {
msupSetChannel:
CFI Block cfiBlock12 Using cfiCommon1
CFI Function msupSetChannel
FUNCALL msupSetChannel, DisableRfInterrupts
LOCFRAME XSTACK, 9, STACK
ARGFRAME XSTACK, 9, STACK
FUNCALL msupSetChannel, mrxResetRxEngine
LOCFRAME XSTACK, 9, STACK
ARGFRAME XSTACK, 9, STACK
FUNCALL msupSetChannel, EnableRfInterrupts
LOCFRAME XSTACK, 9, STACK
ARGFRAME XSTACK, 9, STACK
MOV A,#-0x9
LCALL ?FUNC_ENTER_XDATA
CFI DPH0 load(1, XDATA, add(CFA_XSP16, literal(-1)))
CFI DPL0 load(1, XDATA, add(CFA_XSP16, literal(-2)))
CFI ?RET_HIGH load(1, XDATA, add(CFA_XSP16, literal(-3)))
CFI ?RET_LOW load(1, XDATA, add(CFA_XSP16, literal(-4)))
CFI R7 load(1, XDATA, add(CFA_XSP16, literal(-5)))
CFI V1 load(1, XDATA, add(CFA_XSP16, literal(-6)))
CFI V0 load(1, XDATA, add(CFA_XSP16, literal(-7)))
CFI VB load(1, XDATA, add(CFA_XSP16, literal(-8)))
CFI R6 load(1, XDATA, add(CFA_XSP16, literal(-9)))
CFI CFA_SP SP+0
CFI CFA_XSP16 add(XSP16, 9)
; Saved register size: 9
; Auto size: 0
MOV ?V0 + 0,R1
MOV ?V0 + 1,R2
// 283 UINT16 newFreq, oldFreq;
// 284
// 285 // Derive frequency programming from the given channel number
// 286 newFreq = (UINT16) (logicalChannel - 11); // Subtract the base channel
// 287 newFreq = (UINT16) (newFreq + (newFreq << 2)); // Multiply with 5, which is the channel spacing
// 288 newFreq = (UINT16) (newFreq + 357 + 0x4000); // 357 is 2405-2048, 0x4000 is LOCK_THR = 1
MOV A,R1
MOV B,#0x5
MUL AB
MOV R0,A
MOV R1,B
MOV A,#0x2e
ADD A,R0
MOV R6,A
MOV A,#0x41
ADDC A,R1
MOV R7,A
// 289
// 290 // Do we need to change the frequency at all?
// 291 #pragma diag_suppress=PA082
// 292 oldFreq = READ_RFR16(FSCTRL);
MOV DPTR,#-0x20f0
MOVX A,@DPTR
MOV R1,A
MOV DPTR,#-0x20ef
MOVX A,@DPTR
ADD A,#0x0
MOV R0,A
CLR A
ADDC A,R1
MOV R1,A
// 293 #pragma diag_default=PA082
// 294
// 295 if ((newFreq ^ oldFreq) & 0x03FF) {
MOV A,R0
XRL A,R6
MOV R0,A
MOV A,R1
XRL A,R7
MOV R1,A
MOV A,#0x3
ANL A,R1
MOV R1,A
MOV A,R0
JNZ ??msupSetChannel_0
MOV A,R1
??msupSetChannel_0:
JZ ??msupSetChannel_1
// 296
// 297 // Force RX off
// 298 DISABLE_GLOBAL_INT();
CLR 0xa8.7
// 299 ISRFOFF;
MOV 0xe1,#-0x1b
// 300
// 301 // Clean up if we interrupted the receiver
// 302 DisableRfInterrupts();
; Setup parameters for call to function DisableRfInterrupts
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