📄 mac_cc2430.s51
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CFI CFA_SP SP+-3
CFI DPH0 SameValue
POP DPL
CFI CFA_SP SP+-2
CFI DPL0 SameValue
RET
CFI EndBlock cfiBlock1
// 57
// 58 //-------------------------------------------------------------------------------------------------------
// 59 //
// 60 //-------------------------------------------------------------------------------------------------------
RSEG NEAR_CODE:CODE:NOROOT(0)
// 61 ROOT void FetchDmaChannelConfiguration (BYTE dmaChannelNo,
FetchDmaChannelConfiguration:
CFI Block cfiBlock2 Using cfiCommon0
CFI Function FetchDmaChannelConfiguration
// 62 DMA_CHANNEL_CONFIGURATION **dmaChannelConfiguration)
// 63 {
MOV A,#-0x9
LCALL ?FUNC_ENTER_XDATA
CFI DPH0 load(1, XDATA, add(CFA_XSP16, literal(-1)))
CFI DPL0 load(1, XDATA, add(CFA_XSP16, literal(-2)))
CFI ?RET_HIGH load(1, XDATA, add(CFA_XSP16, literal(-3)))
CFI ?RET_LOW load(1, XDATA, add(CFA_XSP16, literal(-4)))
CFI R7 load(1, XDATA, add(CFA_XSP16, literal(-5)))
CFI V1 load(1, XDATA, add(CFA_XSP16, literal(-6)))
CFI V0 load(1, XDATA, add(CFA_XSP16, literal(-7)))
CFI VB load(1, XDATA, add(CFA_XSP16, literal(-8)))
CFI R6 load(1, XDATA, add(CFA_XSP16, literal(-9)))
CFI CFA_SP SP+0
CFI CFA_XSP16 add(XSP16, 9)
; Saved register size: 9
; Auto size: 0
// 64 *dmaChannelConfiguration = &pDma1234Configs[dmaChannelNo - 1];
MOV ?V0 + 0,R1
MOV ?V0 + 1,#0x0
MOV A,#0x3
MOV R0,#?V0 + 0
LCALL ?S_SHL
MOV A,?V0 + 0
ADD A,#((pDma1234Configs + 248) & 0xff)
MOV R0,A
MOV A,?V0 + 1
ADDC A,#(((pDma1234Configs - 8) >> 8) & 0xff)
MOV R1,A
MOV DPL,R2
MOV DPH,R3
MOV A,R0
MOVX @DPTR,A
INC DPTR
MOV A,R1
MOVX @DPTR,A
// 65 }
MOV R7,#0x2
LJMP ?FUNC_LEAVE_XDATA
CFI EndBlock cfiBlock2
// 66
// 67
// 68 //-------------------------------------------------------------------------------------------------------
// 69 //
// 70 //-------------------------------------------------------------------------------------------------------
RSEG NEAR_CODE:CODE:NOROOT(0)
// 71 ROOT void StartDma (BYTE dmaChannelNo)
StartDma:
CFI Block cfiBlock3 Using cfiCommon0
CFI Function StartDma
// 72 {
PUSH DPL
CFI DPL0 Frame(CFA_SP, 3)
CFI CFA_SP SP+-3
PUSH DPH
CFI DPH0 Frame(CFA_SP, 4)
CFI CFA_SP SP+-4
; Saved register size: 2
; Auto size: 0
// 73 switch (dmaChannelNo)
MOV A,R1
LCALL ?UC_SWITCH_DENSE
`?<Jumptable for StartDma>_0`:
DB 1
DB 3
DW ??StartDma_0
DW ??StartDma_1
DW ??StartDma_2
DW ??StartDma_3
DW ??StartDma_4
// 74 {
// 75
// 76 case DMA_TO_AES_CHANNEL_NO:
// 77 DMAIRQ &= ~DMA_TO_AES_INTERRUPT_MASK;
??StartDma_1:
ANL 0xd1,#0xfd
// 78 DMAARM = DMA_TO_AES_START;
MOV 0xd6,#0x2
SJMP ??StartDma_0
// 79 break;
// 80
// 81 case DMA_FROM_AES_CHANNEL_NO:
// 82 DMAIRQ &= ~DMA_FROM_AES_INTERRUPT_MASK;
??StartDma_2:
ANL 0xd1,#0xfb
// 83 DMAARM = DMA_FROM_AES_START;
MOV 0xd6,#0x4
SJMP ??StartDma_0
// 84 break;
// 85
// 86 case DMA_CHANNEL_NO_3:
// 87 DMAIRQ &= ~DMA_CHANNEL_NO_3_INTERRUPT_MASK;
??StartDma_3:
ANL 0xd1,#0xf7
// 88 DMAARM = DMA_CHANNEL_NO_3_START;
MOV 0xd6,#0x8
// 89 DMAREQ = DMA_CHANNEL_NO_3_START;
MOV 0xd7,#0x8
SJMP ??StartDma_0
// 90 break;
// 91
// 92 case DMA_RFRX_CHANNEL:
// 93 DMAIRQ &= ~DMA_RFRX_CHANNEL_BM;
??StartDma_4:
ANL 0xd1,#0xef
// 94 DMAARM = DMA_RF_START;
MOV 0xd6,#0x10
// 95 DMAREQ = DMA_RF_START;
MOV 0xd7,#0x10
// 96 break;
// 97
// 98 }
// 99 }
??StartDma_0:
SJMP ?Subroutine0
CFI EndBlock cfiBlock3
// 100
// 101 //-------------------------------------------------------------------------------------------------------
// 102 //
// 103 //-------------------------------------------------------------------------------------------------------
// 104 static ROOT void EnableMcuDmaInterrupt (void)
// 105 {
// 106 DMAIF /*IEX7*/ = FALSE;
// 107 DMAIE /*EX7*/ = TRUE;
// 108 }
// 109
// 110 //-------------------------------------------------------------------------------------------------------
// 111 //
// 112 //-------------------------------------------------------------------------------------------------------
// 113 static ROOT void InitializeDmaRf (void)
// 114 {
// 115 pDma1234Configs[DMA_RFRX_CHANNEL - 1].srcMsb = HIBYTE(&X_RFD);
// 116 pDma1234Configs[DMA_RFRX_CHANNEL - 1].srcLsb = LOBYTE(&X_RFD);
// 117 pDma1234Configs[DMA_RFRX_CHANNEL - 1].lenMsb = 0x00;
// 118 pDma1234Configs[DMA_RFRX_CHANNEL - 1].wsizeTmodeTrigger = BYTE_TRANSFER | TRANSFER_MODE_SINGLE | DMA_RF_TRIGGER;
// 119 pDma1234Configs[DMA_RFRX_CHANNEL - 1].incIrqM8Pri = SRC_INC_NONE | DST_INC_ONE_BYTE | DMA_IRQ_ENABLE | DMA_7_BIT_TRANSFER_COUNT | DMA_PRIORITY_LOW;
// 120 }
// 121
// 122 //-------------------------------------------------------------------------------------------------------
// 123 //
// 124 //-------------------------------------------------------------------------------------------------------
// 125 static ROOT void InitializeDmaAes (void)
// 126 {
// 127 DMA_CHANNEL_CONFIGURATION *dmaChannelConfiguration;
// 128
// 129 FetchDmaChannelConfiguration (DMA_TO_AES_CHANNEL_NO, &dmaChannelConfiguration);
// 130
// 131 dmaChannelConfiguration->destMsb = (BYTE)(((WORD) &X_ENCDI) >> 8);
// 132 dmaChannelConfiguration->destLsb = (BYTE)( (WORD) &X_ENCDI);
// 133 dmaChannelConfiguration->lenMsb = USE_LEN;
// 134 dmaChannelConfiguration->wsizeTmodeTrigger = BYTE_TRANSFER +
// 135 TRANSFER_MODE_SINGLE +
// 136 DMA_TO_AES_TRIGGER;
// 137 dmaChannelConfiguration->incIrqM8Pri = SRC_INC_ONE_BYTE +
// 138 DST_INC_NONE +
// 139 DMA_IRQ_DISABLE +
// 140 DMA_8_BIT_TRANSFER_COUNT +
// 141 DMA_PRIORITY_HIGH;
// 142
// 143 FetchDmaChannelConfiguration (DMA_FROM_AES_CHANNEL_NO, &dmaChannelConfiguration);
// 144
// 145 dmaChannelConfiguration->srcMsb = (BYTE)(((WORD) &X_ENCDO) >> 8);
// 146 dmaChannelConfiguration->srcLsb = (BYTE)( (WORD) &X_ENCDO);
// 147 dmaChannelConfiguration->lenMsb = USE_LEN;
// 148 dmaChannelConfiguration->wsizeTmodeTrigger = BYTE_TRANSFER +
// 149 TRANSFER_MODE_SINGLE +
// 150 DMA_FROM_AES_TRIGGER;
// 151 dmaChannelConfiguration->incIrqM8Pri = SRC_INC_NONE +
// 152 DST_INC_ONE_BYTE +
// 153 DMA_IRQ_DISABLE +
// 154 DMA_8_BIT_TRANSFER_COUNT +
// 155 DMA_PRIORITY_HIGH;
// 156
// 157 }
// 158
// 159 //-------------------------------------------------------------------------------------------------------
// 160 //
// 161 // RF routines
// 162 //
// 163 //-------------------------------------------------------------------------------------------------------
// 164 //-------------------------------------------------------------------------------------------------------
// 165 //
// 166 //-------------------------------------------------------------------------------------------------------
RSEG NEAR_CODE:CODE:NOROOT(0)
// 167 ROOT void DisableRfInterrupts (void)
DisableRfInterrupts:
CFI Block cfiBlock4 Using cfiCommon0
CFI Function DisableRfInterrupts
// 168 {
FUNCALL DisableRfInterrupts, SET_RFIM
FUNCALL DisableRfInterrupts, SET_RFIF
; Saved register size: 0
; Auto size: 0
// 169 SET_RFIM(RF_CLEAR_INTERRUPT_MASK);
; Setup parameters for call to function SET_RFIM
MOV R1,#0x0
LCALL SET_RFIM
// 170 SET_RFIF(RF_CLEAR_ALL_INTERRUPTS);
; Setup parameters for call to function SET_RFIF
MOV R1,#0x0
LCALL SET_RFIF
// 171 DisableMcuRfErrInterrupt ();
CLR 0xa8.0
// 172 DisableMcuRfifInterrupt ();
ANL 0x9a,#0xfe
// 173
// 174 }
RET
CFI EndBlock cfiBlock4
// 175
// 176 //-------------------------------------------------------------------------------------------------------
// 177 //
// 178 //-------------------------------------------------------------------------------------------------------
RSEG NEAR_CODE:CODE:NOROOT(0)
// 179 ROOT void EnableRfInterrupts (void)
EnableRfInterrupts:
CFI Block cfiBlock5 Using cfiCommon0
CFI Function EnableRfInterrupts
// 180 {
FUNCALL EnableRfInterrupts, SET_RFIF
FUNCALL EnableRfInterrupts, SET_RFIM
; Saved register size: 0
; Auto size: 0
// 181 SET_RFIF(RF_CLEAR_ALL_INTERRUPTS);
; Setup parameters for call to function SET_RFIF
MOV R1,#0x0
LCALL SET_RFIF
// 182 SET_RFIM(RF_SET_INTERRUPT_MASK);
; Setup parameters for call to function SET_RFIM
MOV R1,#0x62
LCALL SET_RFIM
// 183 EnableMcuRfErrInterrupt ();
CLR 0x88.1
SETB 0xa8.0
// 184 EnableMcuRfifInterrupt ();
MOV 0x9b,#0x0
ORL 0x9a,#0x1
// 185 }
RET
CFI EndBlock cfiBlock5
// 186
// 187 //-------------------------------------------------------------------------------------------------------
// 188 //
// 189 //-------------------------------------------------------------------------------------------------------
// 190 static ROOT void EnableMcuRfErrInterrupt (void)
// 191 {
// 192 RFERRIF /*IE0*/ = FALSE;
// 193 RFERRIE /*EX0*/ = TRUE;
// 194 }
// 195
// 196 //-------------------------------------------------------------------------------------------------------
// 197 //
// 198 //-------------------------------------------------------------------------------------------------------
// 199 static ROOT void EnableMcuRfifInterrupt (void)
// 200 {
// 201 S1CON = FALSE;
// 202 IEN2 |= MCU_RFIF_INTERRUPT_BM;
// 203 }
// 204
// 205 //-------------------------------------------------------------------------------------------------------
// 206 //
// 207 //-------------------------------------------------------------------------------------------------------
// 208 static ROOT void DisableMcuRfErrInterrupt (void)
// 209 {
// 210 RFERRIE /*EX0*/ = FALSE;
// 211 }
// 212
// 213 //-------------------------------------------------------------------------------------------------------
// 214 //
// 215 //-------------------------------------------------------------------------------------------------------
// 216 static ROOT void DisableMcuRfifInterrupt (void)
// 217 {
// 218 IEN2 &= ~MCU_RFIF_INTERRUPT_BM;
// 219 }
// 220
// 221 //-------------------------------------------------------------------------------------------------------
// 222 //
// 223 //-------------------------------------------------------------------------------------------------------
RSEG NEAR_CODE:CODE:NOROOT(0)
// 224 ROOT void InitializeRfInterrupts (void)
InitializeRfInterrupts:
CFI Block cfiBlock6 Using cfiCommon0
CFI Function InitializeRfInterrupts
// 225 {
FUNCALL InitializeRfInterrupts, DisableRfInterrupts
FUNCALL InitializeRfInterrupts, EnableRfInterrupts
; Saved register size: 0
; Auto size: 0
// 226 DisableRfInterrupts ();
; Setup parameters for call to function DisableRfInterrupts
LCALL DisableRfInterrupts
// 227 EnableRfInterrupts ();
; Setup parameters for call to function EnableRfInterrupts
LCALL EnableRfInterrupts
// 228 EnableMcuRfifInterrupt ();
MOV 0x9b,#0x0
ORL 0x9a,#0x1
// 229 EnableMcuRfErrInterrupt ();
CLR 0x88.1
SETB 0xa8.0
// 230 }
RET
CFI EndBlock cfiBlock6
ASEGN SFR_AN:DATA:NOROOT,088H
// union <unnamed> volatile __sfr _A_TCON
_A_TCON:
DS 1
ASEGN SFR_AN:DATA:NOROOT,0a8H
// union <unnamed> volatile __sfr _A_IEN0
_A_IEN0:
DS 1
ASEGN SFR_AN:DATA:NOROOT,0b8H
// union <unnamed> volatile __sfr _A_IEN1
_A_IEN1:
DS 1
ASEGN SFR_AN:DATA:NOROOT,0c0H
// union <unnamed> volatile __sfr _A_IRCON
_A_IRCON:
DS 1
END
//
// 263 bytes in segment NEAR_CODE
// 11 bytes in segment SFR_AN
// 32 bytes in segment XDATA_Z
//
// 263 bytes of CODE memory
// 0 bytes of DATA memory (+ 11 bytes shared)
// 32 bytes of XDATA memory
//
//Errors: none
//Warnings: none
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