my_uart_top.tan.qmsg

关于RS232的VHDL程序

{ "Info" "ITDB_FULL_TCO_RESULT" "clk led1 led11 8.744 ns register " "Info: tco from clock \"clk\" to destination pin \"led1\" through register \"led11\" is 8.744 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 76 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 76; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "my_uart_top.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_top.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns led11 2 REG LC_X2_Y3_N5 2 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X2_Y3_N5; Fanout = 2; REG Node = 'led11'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk led11 } "NODE_NAME" } } { "my_uart_top.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_top.v" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk led11 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} led11 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "my_uart_top.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_top.v" 84 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.020 ns + Longest register pin " "Info: + Longest register to pin delay is 5.020 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led11 1 REG LC_X2_Y3_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y3_N5; Fanout = 2; REG Node = 'led11'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { led11 } "NODE_NAME" } } { "my_uart_top.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_top.v" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.698 ns) + CELL(2.322 ns) 5.020 ns led1 2 PIN PIN_18 0 " "Info: 2: + IC(2.698 ns) + CELL(2.322 ns) = 5.020 ns; Loc. = PIN_18; Fanout = 0; PIN Node = 'led1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.020 ns" { led11 led1 } "NODE_NAME" } } { "my_uart_top.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_top.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 46.25 % ) " "Info: Total cell delay = 2.322 ns ( 46.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.698 ns ( 53.75 % ) " "Info: Total interconnect delay = 2.698 ns ( 53.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.020 ns" { led11 led1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.020 ns" { led11 {} led1 {} } { 0.000ns 2.698ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk led11 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} led11 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.020 ns" { led11 led1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.020 ns" { led11 {} led1 {} } { 0.000ns 2.698ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "my_uart_rx:my_uart_rx\|rx_temp_data\[0\] rs232_rx clk -1.318 ns register " "Info: th for register \"my_uart_rx:my_uart_rx\|rx_temp_data\[0\]\" (data pin = \"rs232_rx\", clock pin = \"clk\") is -1.318 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 76 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 76; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "my_uart_top.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_top.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns my_uart_rx:my_uart_rx\|rx_temp_data\[0\] 2 REG LC_X7_Y3_N3 2 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X7_Y3_N3; Fanout = 2; REG Node = 'my_uart_rx:my_uart_rx\|rx_temp_data\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk my_uart_rx:my_uart_rx|rx_temp_data[0] } "NODE_NAME" } } { "my_uart_rx.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_rx.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk my_uart_rx:my_uart_rx|rx_temp_data[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} my_uart_rx:my_uart_rx|rx_temp_data[0] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "my_uart_rx.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_rx.v" 91 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.887 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.887 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns rs232_rx 1 PIN PIN_78 9 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_78; Fanout = 9; PIN Node = 'rs232_rx'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs232_rx } "NODE_NAME" } } { "my_uart_top.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_top.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.694 ns) + CELL(1.061 ns) 4.887 ns my_uart_rx:my_uart_rx\|rx_temp_data\[0\] 2 REG LC_X7_Y3_N3 2 " "Info: 2: + IC(2.694 ns) + CELL(1.061 ns) = 4.887 ns; Loc. = LC_X7_Y3_N3; Fanout = 2; REG Node = 'my_uart_rx:my_uart_rx\|rx_temp_data\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.755 ns" { rs232_rx my_uart_rx:my_uart_rx|rx_temp_data[0] } "NODE_NAME" } } { "my_uart_rx.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_rx.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.193 ns ( 44.87 % ) " "Info: Total cell delay = 2.193 ns ( 44.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.694 ns ( 55.13 % ) " "Info: Total interconnect delay = 2.694 ns ( 55.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.887 ns" { rs232_rx my_uart_rx:my_uart_rx|rx_temp_data[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.887 ns" { rs232_rx {} rs232_rx~combout {} my_uart_rx:my_uart_rx|rx_temp_data[0] {} } { 0.000ns 0.000ns 2.694ns } { 0.000ns 1.132ns 1.061ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk my_uart_rx:my_uart_rx|rx_temp_data[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} my_uart_rx:my_uart_rx|rx_temp_data[0] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.887 ns" { rs232_rx my_uart_rx:my_uart_rx|rx_temp_data[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.887 ns" { rs232_rx {} rs232_rx~combout {} my_uart_rx:my_uart_rx|rx_temp_data[0] {} } { 0.000ns 0.000ns 2.694ns } { 0.000ns 1.132ns 1.061ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "110 " "Info: Allocated 110 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 10 14:57:13 2009 " "Info: Processing ended: Tue Feb 10 14:57:13 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}