my_uart_top.tan.qmsg

关于RS232的VHDL程序

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "my_uart_top.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_top.v" 27 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register speed_select:speed_rx\|cnt\[8\] register speed_select:speed_rx\|cnt\[12\] 134.25 MHz 7.449 ns Internal " "Info: Clock \"clk\" has Internal fmax of 134.25 MHz between source register \"speed_select:speed_rx\|cnt\[8\]\" and destination register \"speed_select:speed_rx\|cnt\[12\]\" (period= 7.449 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.740 ns + Longest register register " "Info: + Longest register to register delay is 6.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns speed_select:speed_rx\|cnt\[8\] 1 REG LC_X6_Y2_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y2_N2; Fanout = 4; REG Node = 'speed_select:speed_rx\|cnt\[8\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { speed_select:speed_rx|cnt[8] } "NODE_NAME" } } { "speed_select.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/speed_select.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.285 ns) + CELL(0.914 ns) 2.199 ns speed_select:speed_rx\|Equal0~151 2 COMB LC_X6_Y2_N9 2 " "Info: 2: + IC(1.285 ns) + CELL(0.914 ns) = 2.199 ns; Loc. = LC_X6_Y2_N9; Fanout = 2; COMB Node = 'speed_select:speed_rx\|Equal0~151'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.199 ns" { speed_select:speed_rx|cnt[8] speed_select:speed_rx|Equal0~151 } "NODE_NAME" } } { "speed_select.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/speed_select.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.193 ns) + CELL(0.511 ns) 3.903 ns speed_select:speed_rx\|always0~0 3 COMB LC_X5_Y2_N2 13 " "Info: 3: + IC(1.193 ns) + CELL(0.511 ns) = 3.903 ns; Loc. = LC_X5_Y2_N2; Fanout = 13; COMB Node = 'speed_select:speed_rx\|always0~0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.704 ns" { speed_select:speed_rx|Equal0~151 speed_select:speed_rx|always0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.077 ns) + CELL(1.760 ns) 6.740 ns speed_select:speed_rx\|cnt\[12\] 4 REG LC_X6_Y2_N6 3 " "Info: 4: + IC(1.077 ns) + CELL(1.760 ns) = 6.740 ns; Loc. = LC_X6_Y2_N6; Fanout = 3; REG Node = 'speed_select:speed_rx\|cnt\[12\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.837 ns" { speed_select:speed_rx|always0~0 speed_select:speed_rx|cnt[12] } "NODE_NAME" } } { "speed_select.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/speed_select.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.185 ns ( 47.26 % ) " "Info: Total cell delay = 3.185 ns ( 47.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.555 ns ( 52.74 % ) " "Info: Total interconnect delay = 3.555 ns ( 52.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.740 ns" { speed_select:speed_rx|cnt[8] speed_select:speed_rx|Equal0~151 speed_select:speed_rx|always0~0 speed_select:speed_rx|cnt[12] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.740 ns" { speed_select:speed_rx|cnt[8] {} speed_select:speed_rx|Equal0~151 {} speed_select:speed_rx|always0~0 {} speed_select:speed_rx|cnt[12] {} } { 0.000ns 1.285ns 1.193ns 1.077ns } { 0.000ns 0.914ns 0.511ns 1.760ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 76 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 76; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "my_uart_top.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_top.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns speed_select:speed_rx\|cnt\[12\] 2 REG LC_X6_Y2_N6 3 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y2_N6; Fanout = 3; REG Node = 'speed_select:speed_rx\|cnt\[12\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk speed_select:speed_rx|cnt[12] } "NODE_NAME" } } { "speed_select.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/speed_select.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk speed_select:speed_rx|cnt[12] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} speed_select:speed_rx|cnt[12] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 76 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 76; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "my_uart_top.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_top.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns speed_select:speed_rx\|cnt\[8\] 2 REG LC_X6_Y2_N2 4 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y2_N2; Fanout = 4; REG Node = 'speed_select:speed_rx\|cnt\[8\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk speed_select:speed_rx|cnt[8] } "NODE_NAME" } } { "speed_select.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/speed_select.v" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk speed_select:speed_rx|cnt[8] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} speed_select:speed_rx|cnt[8] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk speed_select:speed_rx|cnt[12] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} speed_select:speed_rx|cnt[12] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk speed_select:speed_rx|cnt[8] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} speed_select:speed_rx|cnt[8] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "speed_select.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/speed_select.v" 58 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "speed_select.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/speed_select.v" 58 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.740 ns" { speed_select:speed_rx|cnt[8] speed_select:speed_rx|Equal0~151 speed_select:speed_rx|always0~0 speed_select:speed_rx|cnt[12] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.740 ns" { speed_select:speed_rx|cnt[8] {} speed_select:speed_rx|Equal0~151 {} speed_select:speed_rx|always0~0 {} speed_select:speed_rx|cnt[12] {} } { 0.000ns 1.285ns 1.193ns 1.077ns } { 0.000ns 0.914ns 0.511ns 1.760ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk speed_select:speed_rx|cnt[12] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} speed_select:speed_rx|cnt[12] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk speed_select:speed_rx|cnt[8] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} speed_select:speed_rx|cnt[8] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "my_uart_rx:my_uart_rx\|rx_temp_data\[6\] rs232_rx clk 2.132 ns register " "Info: tsu for register \"my_uart_rx:my_uart_rx\|rx_temp_data\[6\]\" (data pin = \"rs232_rx\", clock pin = \"clk\") is 2.132 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.147 ns + Longest pin register " "Info: + Longest pin to register delay is 5.147 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns rs232_rx 1 PIN PIN_78 9 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_78; Fanout = 9; PIN Node = 'rs232_rx'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rs232_rx } "NODE_NAME" } } { "my_uart_top.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_top.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.954 ns) + CELL(1.061 ns) 5.147 ns my_uart_rx:my_uart_rx\|rx_temp_data\[6\] 2 REG LC_X5_Y3_N1 2 " "Info: 2: + IC(2.954 ns) + CELL(1.061 ns) = 5.147 ns; Loc. = LC_X5_Y3_N1; Fanout = 2; REG Node = 'my_uart_rx:my_uart_rx\|rx_temp_data\[6\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.015 ns" { rs232_rx my_uart_rx:my_uart_rx|rx_temp_data[6] } "NODE_NAME" } } { "my_uart_rx.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_rx.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.193 ns ( 42.61 % ) " "Info: Total cell delay = 2.193 ns ( 42.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.954 ns ( 57.39 % ) " "Info: Total interconnect delay = 2.954 ns ( 57.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.147 ns" { rs232_rx my_uart_rx:my_uart_rx|rx_temp_data[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.147 ns" { rs232_rx {} rs232_rx~combout {} my_uart_rx:my_uart_rx|rx_temp_data[6] {} } { 0.000ns 0.000ns 2.954ns } { 0.000ns 1.132ns 1.061ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "my_uart_rx.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_rx.v" 91 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 76 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 76; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "my_uart_top.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_top.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns my_uart_rx:my_uart_rx\|rx_temp_data\[6\] 2 REG LC_X5_Y3_N1 2 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y3_N1; Fanout = 2; REG Node = 'my_uart_rx:my_uart_rx\|rx_temp_data\[6\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk my_uart_rx:my_uart_rx|rx_temp_data[6] } "NODE_NAME" } } { "my_uart_rx.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_rx.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk my_uart_rx:my_uart_rx|rx_temp_data[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} my_uart_rx:my_uart_rx|rx_temp_data[6] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.147 ns" { rs232_rx my_uart_rx:my_uart_rx|rx_temp_data[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.147 ns" { rs232_rx {} rs232_rx~combout {} my_uart_rx:my_uart_rx|rx_temp_data[6] {} } { 0.000ns 0.000ns 2.954ns } { 0.000ns 1.132ns 1.061ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk my_uart_rx:my_uart_rx|rx_temp_data[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} my_uart_rx:my_uart_rx|rx_temp_data[6] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}