prev_cmp_my_uart_top.qmsg

关于RS232的VHDL程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 10 14:55:56 2009 " "Info: Processing started: Tue Feb 10 14:55:56 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off my_uart_top -c my_uart_top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off my_uart_top -c my_uart_top" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "my_uart_rx.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file my_uart_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 my_uart_rx " "Info: Found entity 1: my_uart_rx" {  } { { "my_uart_rx.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_rx.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "my_uart_top.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file my_uart_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 my_uart_top " "Info: Found entity 1: my_uart_top" {  } { { "my_uart_top.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_top.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "my_uart_tx.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file my_uart_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 my_uart_tx " "Info: Found entity 1: my_uart_tx" {  } { { "my_uart_tx.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_tx.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "speed_select.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file speed_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 speed_select " "Info: Found entity 1: speed_select" {  } { { "speed_select.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/speed_select.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "my_uart_top " "Info: Elaborating entity \"my_uart_top\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "speed_select speed_select:speed_rx " "Info: Elaborating entity \"speed_select\" for hierarchy \"speed_select:speed_rx\"" {  } { { "my_uart_top.v" "speed_rx" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_top.v" 46 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "my_uart_rx my_uart_rx:my_uart_rx " "Info: Elaborating entity \"my_uart_rx\" for hierarchy \"my_uart_rx:my_uart_rx\"" {  } { { "my_uart_top.v" "my_uart_rx" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_top.v" 56 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "my_uart_tx my_uart_tx:my_uart_tx " "Info: Elaborating entity \"my_uart_tx\" for hierarchy \"my_uart_tx:my_uart_tx\"" {  } { { "my_uart_top.v" "my_uart_tx" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_top.v" 74 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "my_uart_tx:my_uart_tx\|bps_start " "Warning: Converting TRI node \"my_uart_tx:my_uart_tx\|bps_start\" that feeds logic to a wire" {  } { { "my_uart_tx.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_tx.v" 33 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0 "" 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "my_uart_rx:my_uart_rx\|bps_start " "Warning: Converting TRI node \"my_uart_rx:my_uart_rx\|bps_start\" that feeds logic to a wire" {  } { { "my_uart_rx.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_rx.v" 31 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0 "" 0}  } {  } 0 0 "Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" 0 0 "" 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "my_uart_tx.v" "" { Text "D:/学习版/例程/9743027c-f830-4617-987d-72490f9ccbe5/uartverilog/my_uart_tx.v" 88 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 2 " "Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "my_uart_tx:my_uart_tx\|bps_start_r~en " "Info: Register \"my_uart_tx:my_uart_tx\|bps_start_r~en\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "my_uart_rx:my_uart_rx\|bps_start_r~en " "Info: Register \"my_uart_rx:my_uart_rx\|bps_start_r~en\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "131 " "Info: Implemented 131 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "123 " "Info: Implemented 123 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "140 " "Info: Allocated 140 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 10 14:55:59 2009 " "Info: Processing ended: Tue Feb 10 14:55:59 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}