pwm_gen.tan.qmsg

pwm模块pwm模块pwm模块pwm模块pwm模块

{ "Info" "ITDB_FULL_TCO_RESULT" "clock_24M tx serialport_tx:inst5\|tx 13.400 ns register " "Info: tco from clock \"clock_24M\" to destination pin \"tx\" through register \"serialport_tx:inst5\|tx\" is 13.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M source 10.200 ns + Longest register " "Info: + Longest clock path from clock \"clock_24M\" to source register is 10.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 55 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 55; CLK Node = 'clock_24M'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock_24M } "NODE_NAME" } } { "pwm_gen.bdf" "" { Schematic "D:/bysj/PWM2/13-PWM信号产生/pwm_gen.bdf" { { 152 0 168 168 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns counter:inst3\|carrier 2 REG LC58 49 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC58; Fanout = 49; REG Node = 'counter:inst3\|carrier'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { clock_24M counter:inst3|carrier } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/counter.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.200 ns) 10.200 ns serialport_tx:inst5\|tx 3 REG LC6 1 " "Info: 3: + IC(3.000 ns) + CELL(2.200 ns) = 10.200 ns; Loc. = LC6; Fanout = 1; REG Node = 'serialport_tx:inst5\|tx'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.200 ns" { counter:inst3|carrier serialport_tx:inst5|tx } "NODE_NAME" } } { "serialport_tx.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/serialport_tx.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 70.59 % ) " "Info: Total cell delay = 7.200 ns ( 70.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns ( 29.41 % ) " "Info: Total interconnect delay = 3.000 ns ( 29.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "10.200 ns" { clock_24M counter:inst3|carrier serialport_tx:inst5|tx } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "10.200 ns" { clock_24M {} clock_24M~out {} counter:inst3|carrier {} serialport_tx:inst5|tx {} } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 2.500ns 2.500ns 2.200ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "serialport_tx.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/serialport_tx.vhd" 41 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.600 ns + Longest register pin " "Info: + Longest register to pin delay is 1.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns serialport_tx:inst5\|tx 1 REG LC6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6; Fanout = 1; REG Node = 'serialport_tx:inst5\|tx'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { serialport_tx:inst5|tx } "NODE_NAME" } } { "serialport_tx.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/serialport_tx.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns tx 2 PIN PIN_99 0 " "Info: 2: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_99; Fanout = 0; PIN Node = 'tx'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { serialport_tx:inst5|tx tx } "NODE_NAME" } } { "pwm_gen.bdf" "" { Schematic "D:/bysj/PWM2/13-PWM信号产生/pwm_gen.bdf" { { 304 784 960 320 "tx" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 100.00 % ) " "Info: Total cell delay = 1.600 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { serialport_tx:inst5|tx tx } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.600 ns" { serialport_tx:inst5|tx {} tx {} } { 0.000ns 0.000ns } { 0.000ns 1.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "10.200 ns" { clock_24M counter:inst3|carrier serialport_tx:inst5|tx } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "10.200 ns" { clock_24M {} clock_24M~out {} counter:inst3|carrier {} serialport_tx:inst5|tx {} } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 2.500ns 2.500ns 2.200ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { serialport_tx:inst5|tx tx } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.600 ns" { serialport_tx:inst5|tx {} tx {} } { 0.000ns 0.000ns } { 0.000ns 1.600ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "pwm_counter:inst\|send_timer reset clock_24M -0.800 ns register " "Info: th for register \"pwm_counter:inst\|send_timer\" (data pin = \"reset\", clock pin = \"clock_24M\") is -0.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M destination 3.400 ns + Longest register " "Info: + Longest clock path from clock \"clock_24M\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 55 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 55; CLK Node = 'clock_24M'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock_24M } "NODE_NAME" } } { "pwm_gen.bdf" "" { Schematic "D:/bysj/PWM2/13-PWM信号产生/pwm_gen.bdf" { { 152 0 168 168 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns pwm_counter:inst\|send_timer 2 REG LC39 67 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC39; Fanout = 67; REG Node = 'pwm_counter:inst\|send_timer'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.900 ns" { clock_24M pwm_counter:inst|send_timer } "NODE_NAME" } } { "pwm_counter.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/pwm_counter.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { clock_24M pwm_counter:inst|send_timer } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M {} clock_24M~out {} pwm_counter:inst|send_timer {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "pwm_counter.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/pwm_counter.vhd" 59 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.500 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns reset 1 PIN PIN_89 103 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_89; Fanout = 103; PIN Node = 'reset'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "pwm_gen.bdf" "" { Schematic "D:/bysj/PWM2/13-PWM信号产生/pwm_gen.bdf" { { 168 0 168 184 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(1.300 ns) 5.500 ns pwm_counter:inst\|send_timer 2 REG LC39 67 " "Info: 2: + IC(1.700 ns) + CELL(1.300 ns) = 5.500 ns; Loc. = LC39; Fanout = 67; REG Node = 'pwm_counter:inst\|send_timer'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { reset pwm_counter:inst|send_timer } "NODE_NAME" } } { "pwm_counter.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/pwm_counter.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns ( 69.09 % ) " "Info: Total cell delay = 3.800 ns ( 69.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns ( 30.91 % ) " "Info: Total interconnect delay = 1.700 ns ( 30.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.500 ns" { reset pwm_counter:inst|send_timer } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.500 ns" { reset {} reset~out {} pwm_counter:inst|send_timer {} } { 0.000ns 0.000ns 1.700ns } { 0.000ns 2.500ns 1.300ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { clock_24M pwm_counter:inst|send_timer } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M {} clock_24M~out {} pwm_counter:inst|send_timer {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.500 ns" { reset pwm_counter:inst|send_timer } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.500 ns" { reset {} reset~out {} pwm_counter:inst|send_timer {} } { 0.000ns 0.000ns 1.700ns } { 0.000ns 2.500ns 1.300ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 4 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "120 " "Info: Peak virtual memory: 120 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 13 15:22:38 2009 " "Info: Processing ended: Mon Apr 13 15:22:38 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}