pwm_gen.tan.qmsg

pwm模块pwm模块pwm模块pwm模块pwm模块

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock_24M register pwm_counter:inst\|byte_index\[4\] register serialport_tx:inst5\|idata\[6\] 47.17 MHz 21.2 ns Internal " "Info: Clock \"clock_24M\" has Internal fmax of 47.17 MHz between source register \"pwm_counter:inst\|byte_index\[4\]\" and destination register \"serialport_tx:inst5\|idata\[6\]\" (period= 21.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.900 ns + Longest register register " "Info: + Longest register to register delay is 12.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pwm_counter:inst\|byte_index\[4\] 1 REG LC47 20 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC47; Fanout = 20; REG Node = 'pwm_counter:inst\|byte_index\[4\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { pwm_counter:inst|byte_index[4] } "NODE_NAME" } } { "pwm_counter.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/pwm_counter.vhd" 127 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(4.400 ns) 7.200 ns serialport_tx:inst5\|idata~728 2 COMB LC86 2 " "Info: 2: + IC(2.800 ns) + CELL(4.400 ns) = 7.200 ns; Loc. = LC86; Fanout = 2; COMB Node = 'serialport_tx:inst5\|idata~728'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.200 ns" { pwm_counter:inst|byte_index[4] serialport_tx:inst5|idata~728 } "NODE_NAME" } } { "serialport_tx.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/serialport_tx.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(3.100 ns) 12.900 ns serialport_tx:inst5\|idata\[6\] 3 REG LC3 5 " "Info: 3: + IC(2.600 ns) + CELL(3.100 ns) = 12.900 ns; Loc. = LC3; Fanout = 5; REG Node = 'serialport_tx:inst5\|idata\[6\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.700 ns" { serialport_tx:inst5|idata~728 serialport_tx:inst5|idata[6] } "NODE_NAME" } } { "serialport_tx.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/serialport_tx.vhd" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.500 ns ( 58.14 % ) " "Info: Total cell delay = 7.500 ns ( 58.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.400 ns ( 41.86 % ) " "Info: Total interconnect delay = 5.400 ns ( 41.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "12.900 ns" { pwm_counter:inst|byte_index[4] serialport_tx:inst5|idata~728 serialport_tx:inst5|idata[6] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "12.900 ns" { pwm_counter:inst|byte_index[4] {} serialport_tx:inst5|idata~728 {} serialport_tx:inst5|idata[6] {} } { 0.000ns 2.800ns 2.600ns } { 0.000ns 4.400ns 3.100ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "6.800 ns - Smallest " "Info: - Smallest clock skew is 6.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M destination 10.200 ns + Shortest register " "Info: + Shortest clock path from clock \"clock_24M\" to destination register is 10.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 55 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 55; CLK Node = 'clock_24M'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock_24M } "NODE_NAME" } } { "pwm_gen.bdf" "" { Schematic "D:/bysj/PWM2/13-PWM信号产生/pwm_gen.bdf" { { 152 0 168 168 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns counter:inst3\|carrier 2 REG LC58 49 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC58; Fanout = 49; REG Node = 'counter:inst3\|carrier'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { clock_24M counter:inst3|carrier } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/counter.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.200 ns) 10.200 ns serialport_tx:inst5\|idata\[6\] 3 REG LC3 5 " "Info: 3: + IC(3.000 ns) + CELL(2.200 ns) = 10.200 ns; Loc. = LC3; Fanout = 5; REG Node = 'serialport_tx:inst5\|idata\[6\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.200 ns" { counter:inst3|carrier serialport_tx:inst5|idata[6] } "NODE_NAME" } } { "serialport_tx.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/serialport_tx.vhd" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 70.59 % ) " "Info: Total cell delay = 7.200 ns ( 70.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns ( 29.41 % ) " "Info: Total interconnect delay = 3.000 ns ( 29.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "10.200 ns" { clock_24M counter:inst3|carrier serialport_tx:inst5|idata[6] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "10.200 ns" { clock_24M {} clock_24M~out {} counter:inst3|carrier {} serialport_tx:inst5|idata[6] {} } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 2.500ns 2.500ns 2.200ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M source 3.400 ns - Longest register " "Info: - Longest clock path from clock \"clock_24M\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 55 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 55; CLK Node = 'clock_24M'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock_24M } "NODE_NAME" } } { "pwm_gen.bdf" "" { Schematic "D:/bysj/PWM2/13-PWM信号产生/pwm_gen.bdf" { { 152 0 168 168 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns pwm_counter:inst\|byte_index\[4\] 2 REG LC47 20 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC47; Fanout = 20; REG Node = 'pwm_counter:inst\|byte_index\[4\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.900 ns" { clock_24M pwm_counter:inst|byte_index[4] } "NODE_NAME" } } { "pwm_counter.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/pwm_counter.vhd" 127 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { clock_24M pwm_counter:inst|byte_index[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M {} clock_24M~out {} pwm_counter:inst|byte_index[4] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "10.200 ns" { clock_24M counter:inst3|carrier serialport_tx:inst5|idata[6] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "10.200 ns" { clock_24M {} clock_24M~out {} counter:inst3|carrier {} serialport_tx:inst5|idata[6] {} } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 2.500ns 2.500ns 2.200ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { clock_24M pwm_counter:inst|byte_index[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M {} clock_24M~out {} pwm_counter:inst|byte_index[4] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "pwm_counter.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/pwm_counter.vhd" 127 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "serialport_tx.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/serialport_tx.vhd" 64 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "pwm_counter.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/pwm_counter.vhd" 127 -1 0 } } { "serialport_tx.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/serialport_tx.vhd" 64 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "12.900 ns" { pwm_counter:inst|byte_index[4] serialport_tx:inst5|idata~728 serialport_tx:inst5|idata[6] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "12.900 ns" { pwm_counter:inst|byte_index[4] {} serialport_tx:inst5|idata~728 {} serialport_tx:inst5|idata[6] {} } { 0.000ns 2.800ns 2.600ns } { 0.000ns 4.400ns 3.100ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "10.200 ns" { clock_24M counter:inst3|carrier serialport_tx:inst5|idata[6] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "10.200 ns" { clock_24M {} clock_24M~out {} counter:inst3|carrier {} serialport_tx:inst5|idata[6] {} } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 2.500ns 2.500ns 2.200ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { clock_24M pwm_counter:inst|byte_index[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M {} clock_24M~out {} pwm_counter:inst|byte_index[4] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clock_24M 38 " "Warning: Circuit may not operate. Detected 38 non-operational path(s) clocked by clock \"clock_24M\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "pwm_counter:inst\|byte_index\[4\] serialport_tx:inst5\|idata\[4\] clock_24M 600 ps " "Info: Found hold time violation between source  pin or register \"pwm_counter:inst\|byte_index\[4\]\" and destination pin or register \"serialport_tx:inst5\|idata\[4\]\" for clock \"clock_24M\" (Hold time is 600 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "6.800 ns + Largest " "Info: + Largest clock skew is 6.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M destination 10.200 ns + Longest register " "Info: + Longest clock path from clock \"clock_24M\" to destination register is 10.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 55 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 55; CLK Node = 'clock_24M'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock_24M } "NODE_NAME" } } { "pwm_gen.bdf" "" { Schematic "D:/bysj/PWM2/13-PWM信号产生/pwm_gen.bdf" { { 152 0 168 168 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns counter:inst3\|carrier 2 REG LC58 49 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC58; Fanout = 49; REG Node = 'counter:inst3\|carrier'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { clock_24M counter:inst3|carrier } "NODE_NAME" } } { "counter.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/counter.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.200 ns) 10.200 ns serialport_tx:inst5\|idata\[4\] 3 REG LC14 5 " "Info: 3: + IC(3.000 ns) + CELL(2.200 ns) = 10.200 ns; Loc. = LC14; Fanout = 5; REG Node = 'serialport_tx:inst5\|idata\[4\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.200 ns" { counter:inst3|carrier serialport_tx:inst5|idata[4] } "NODE_NAME" } } { "serialport_tx.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/serialport_tx.vhd" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns ( 70.59 % ) " "Info: Total cell delay = 7.200 ns ( 70.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns ( 29.41 % ) " "Info: Total interconnect delay = 3.000 ns ( 29.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "10.200 ns" { clock_24M counter:inst3|carrier serialport_tx:inst5|idata[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "10.200 ns" { clock_24M {} clock_24M~out {} counter:inst3|carrier {} serialport_tx:inst5|idata[4] {} } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 2.500ns 2.500ns 2.200ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M source 3.400 ns - Shortest register " "Info: - Shortest clock path from clock \"clock_24M\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 55 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 55; CLK Node = 'clock_24M'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock_24M } "NODE_NAME" } } { "pwm_gen.bdf" "" { Schematic "D:/bysj/PWM2/13-PWM信号产生/pwm_gen.bdf" { { 152 0 168 168 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns pwm_counter:inst\|byte_index\[4\] 2 REG LC47 20 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC47; Fanout = 20; REG Node = 'pwm_counter:inst\|byte_index\[4\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.900 ns" { clock_24M pwm_counter:inst|byte_index[4] } "NODE_NAME" } } { "pwm_counter.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/pwm_counter.vhd" 127 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { clock_24M pwm_counter:inst|byte_index[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M {} clock_24M~out {} pwm_counter:inst|byte_index[4] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "10.200 ns" { clock_24M counter:inst3|carrier serialport_tx:inst5|idata[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "10.200 ns" { clock_24M {} clock_24M~out {} counter:inst3|carrier {} serialport_tx:inst5|idata[4] {} } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 2.500ns 2.500ns 2.200ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { clock_24M pwm_counter:inst|byte_index[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M {} clock_24M~out {} pwm_counter:inst|byte_index[4] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns - " "Info: - Micro clock to output delay of source is 1.600 ns" {  } { { "pwm_counter.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/pwm_counter.vhd" 127 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.900 ns - Shortest register register " "Info: - Shortest register to register delay is 5.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pwm_counter:inst\|byte_index\[4\] 1 REG LC47 20 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC47; Fanout = 20; REG Node = 'pwm_counter:inst\|byte_index\[4\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { pwm_counter:inst|byte_index[4] } "NODE_NAME" } } { "pwm_counter.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/pwm_counter.vhd" 127 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(3.100 ns) 5.900 ns serialport_tx:inst5\|idata\[4\] 2 REG LC14 5 " "Info: 2: + IC(2.800 ns) + CELL(3.100 ns) = 5.900 ns; Loc. = LC14; Fanout = 5; REG Node = 'serialport_tx:inst5\|idata\[4\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { pwm_counter:inst|byte_index[4] serialport_tx:inst5|idata[4] } "NODE_NAME" } } { "serialport_tx.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/serialport_tx.vhd" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.100 ns ( 52.54 % ) " "Info: Total cell delay = 3.100 ns ( 52.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns ( 47.46 % ) " "Info: Total interconnect delay = 2.800 ns ( 47.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { pwm_counter:inst|byte_index[4] serialport_tx:inst5|idata[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.900 ns" { pwm_counter:inst|byte_index[4] {} serialport_tx:inst5|idata[4] {} } { 0.000ns 2.800ns } { 0.000ns 3.100ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "serialport_tx.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/serialport_tx.vhd" 64 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "pwm_counter.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/pwm_counter.vhd" 127 -1 0 } } { "serialport_tx.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/serialport_tx.vhd" 64 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "10.200 ns" { clock_24M counter:inst3|carrier serialport_tx:inst5|idata[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "10.200 ns" { clock_24M {} clock_24M~out {} counter:inst3|carrier {} serialport_tx:inst5|idata[4] {} } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 2.500ns 2.500ns 2.200ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { clock_24M pwm_counter:inst|byte_index[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M {} clock_24M~out {} pwm_counter:inst|byte_index[4] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { pwm_counter:inst|byte_index[4] serialport_tx:inst5|idata[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.900 ns" { pwm_counter:inst|byte_index[4] {} serialport_tx:inst5|idata[4] {} } { 0.000ns 2.800ns } { 0.000ns 3.100ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "pwm_counter:inst\|send_timer reset clock_24M 5.000 ns register " "Info: tsu for register \"pwm_counter:inst\|send_timer\" (data pin = \"reset\", clock pin = \"clock_24M\") is 5.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.500 ns + Longest pin register " "Info: + Longest pin to register delay is 5.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns reset 1 PIN PIN_89 103 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_89; Fanout = 103; PIN Node = 'reset'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "pwm_gen.bdf" "" { Schematic "D:/bysj/PWM2/13-PWM信号产生/pwm_gen.bdf" { { 168 0 168 184 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(1.300 ns) 5.500 ns pwm_counter:inst\|send_timer 2 REG LC39 67 " "Info: 2: + IC(1.700 ns) + CELL(1.300 ns) = 5.500 ns; Loc. = LC39; Fanout = 67; REG Node = 'pwm_counter:inst\|send_timer'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { reset pwm_counter:inst|send_timer } "NODE_NAME" } } { "pwm_counter.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/pwm_counter.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns ( 69.09 % ) " "Info: Total cell delay = 3.800 ns ( 69.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns ( 30.91 % ) " "Info: Total interconnect delay = 1.700 ns ( 30.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.500 ns" { reset pwm_counter:inst|send_timer } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.500 ns" { reset {} reset~out {} pwm_counter:inst|send_timer {} } { 0.000ns 0.000ns 1.700ns } { 0.000ns 2.500ns 1.300ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "pwm_counter.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/pwm_counter.vhd" 59 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_24M destination 3.400 ns - Shortest register " "Info: - Shortest clock path from clock \"clock_24M\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clock_24M 1 CLK PIN_87 55 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 55; CLK Node = 'clock_24M'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock_24M } "NODE_NAME" } } { "pwm_gen.bdf" "" { Schematic "D:/bysj/PWM2/13-PWM信号产生/pwm_gen.bdf" { { 152 0 168 168 "clock_24M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns pwm_counter:inst\|send_timer 2 REG LC39 67 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC39; Fanout = 67; REG Node = 'pwm_counter:inst\|send_timer'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.900 ns" { clock_24M pwm_counter:inst|send_timer } "NODE_NAME" } } { "pwm_counter.vhd" "" { Text "D:/bysj/PWM2/13-PWM信号产生/pwm_counter.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 100.00 % ) " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { clock_24M pwm_counter:inst|send_timer } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M {} clock_24M~out {} pwm_counter:inst|send_timer {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.500 ns" { reset pwm_counter:inst|send_timer } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.500 ns" { reset {} reset~out {} pwm_counter:inst|send_timer {} } { 0.000ns 0.000ns 1.700ns } { 0.000ns 2.500ns 1.300ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { clock_24M pwm_counter:inst|send_timer } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.400 ns" { clock_24M {} clock_24M~out {} pwm_counter:inst|send_timer {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}