ad_ad7980fifo.vhd

DSP并行读取串行接口A/D芯片的VHDL接口程序

-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
entity AD_AD7980FIFO is
  port 
  (
     reset,clk,csad,ea2,write,read,ad_din		: in  std_logic;
     dspclk		: in std_logic;
     ad_cnv,clk_out								: out Std_Logic;
		 hfull		: OUT STD_LOGIC ;
--     datain											: in Std_Logic_Vector(15 downto 0);
--     dataout											: out Std_Logic_Vector(15 downto 0)	
     data											: inout Std_Logic_Vector(15 downto 0)	
  );
end entity; 

architecture Behaviour of AD_AD7980FIFO is

	component divde_freq is port 
  (
     reset,clk,cssetup,write		: in  std_logic;
     datain				: in std_logic_vector(15 downto 0);	
     clkout			 	: out std_logic
  );
	end component; 

	component FIFO_DC1K16 IS PORT
  (
  	Data: in  std_logic_vector(15 downto 0); 
		WrClock: in  std_logic; 
		RdClock: in  std_logic; 
		WrEn: in  std_logic; 
		RdEn: in  std_logic; 
		Reset: in  std_logic; 
		RPReset: in  std_logic; 
		Q: out  std_logic_vector(15 downto 0); 
		Empty: out  std_logic; 
		Full: out  std_logic;
		AlmostFull: out  std_logic
	);
	end component;


  signal ad_value,ad_valueout     	: Std_Logic_Vector(15 downto 0); 
  signal shiften,shiften1,shiften2 	: Std_Logic;
  signal shift_cnt					: Std_Logic_Vector(4 downto 0);
  signal rclk,csadrd				: std_logic;
  signal cssetup,adclk,tmp1,tmp2		: std_logic;
	signal reseth,wr_fifo,drdfifo	: std_logic;
	signal data_out		: std_logic_vector(15 downto 0);
--	signal wrusedw		: std_logic_vector(10 downto 0);
	signal rdempty,wrfull,AlmostFull		: STD_LOGIC ;
	signal shiften3,shiften4 	: Std_Logic;
	
begin
	
	reseth <= not reset;
	csadrd <= csad or ea2 or read;
	cssetup <= csad or (not ea2);
	
	clk_out <= not (shiften1) or (not clk) or shiften2;
--  rclk <= not (shiften1) or (not clk) or shiften2;
	rclk <= shiften3 and  clk and (not shiften4);

--  process(reset,shift_cnt)
  process(reset,adclk,shift_cnt)
  begin
  	if reset = '0' or shift_cnt="10101" then			--10110
  		shiften <= '0';
 	  elsif adclk = '0' then
  		shiften <='1';
  	end if;
  end process;
 
	process(reset,AlmostFull,dspclk)
	begin
		if(reset='0')then   
		  hfull <= '0';
		elsif(dspclk'event and dspclk='1')then  
			hfull <= AlmostFull;
		end if;
	end process; 

	process(reset,csadrd,dspclk)
	begin
		if(reset='0')then   
		  tmp1 <= '1'; 
		  tmp2 <= '1';
		  drdfifo <= '0';
		elsif(dspclk'event and dspclk='1')then  
		  tmp2 <= tmp1;
		  tmp1 <= csadrd;
		  drdfifo <= tmp2 and (not tmp1); 
		end if;
	end process; 
 
	process(clk,shiften,shift_cnt)
	begin
  	if shiften = '0' then
  		shift_cnt <= "00000";
	  	ad_cnv <= '1';
	  	shiften1 <= '0';
	  	wr_fifo <= '0';
	  	shiften3 <= '0';
  	elsif	clk'event and clk='1' then
			case shift_cnt is
			  when "00001" =>
			  	ad_cnv <= '0';
			  when "00010" =>
			  	shiften1 <= '1';
--			  when "00011" =>
			  	shiften3 <= '1';
			 	when "10001" =>			--10010
					shiften1 <= '0';
			 	when "10010" =>			--10011
					ad_cnv <= '1';	
					shiften3 <= '0';
					ad_valueout <= ad_value;
				when "10011" =>			--10100
					wr_fifo <= '1';
				when others =>

			end case;
			shift_cnt <= shift_cnt + '1';
		end if;
  end process;
  
  process(clk,shiften,shift_cnt)
	begin
  	if shiften = '0' then
	  	shiften2 <= '0';
  	elsif	clk'event and clk='0' then
			if shift_cnt="10001" then			--10010
			  shiften2 <= '1';
			end if;
		end if;
  end process;

	process(clk,shiften,shift_cnt)
	begin
  	if shiften = '0' then
	  	shiften4 <= '0';
  	elsif	clk'event and clk='0' then
			if shift_cnt="10010" then			--10011
			  shiften4 <= '1';
			end if;
		end if;
  end process;

	process(rclk,ad_din)
	begin
  	if	rclk'event and rclk='1' then
	  	ad_value(15) <= ad_value(14);
	  	ad_value(14) <= ad_value(13);	  	
	  	ad_value(13) <= ad_value(12);
	  	ad_value(12) <= ad_value(11);
	  	ad_value(11) <= ad_value(10);	  	
	  	ad_value(10) <= ad_value(9);
	  	ad_value(9) <= ad_value(8);
	  	ad_value(8) <= ad_value(7);	  	
	  	ad_value(7) <= ad_value(6);
	  	ad_value(6) <= ad_value(5);
	  	ad_value(5) <= ad_value(4);	  	
	  	ad_value(4) <= ad_value(3);
	  	ad_value(3) <= ad_value(2);
	  	ad_value(2) <= ad_value(1);	  	
	  	ad_value(1) <= ad_value(0);
	  	ad_value(0) <= ad_din;
		end if;
  end process;

	process(csadrd,data_out)
  begin
  	if csadrd='0' then
  		data <= data_out;
 	  else
  		data <= (others => 'Z');
  	end if;
  end process;

	clk_div: component divde_freq port map
  (
     reset	=> reset,
     clk		=> clk,
     cssetup	=> cssetup,
     write		=> write,
     datain		=> data,
     clkout		=> adclk
  );

	FIFO:component FIFO_DC1K16 PORT map
	(
		Data			=> ad_valueout, 
		WrClock		=> clk, 
		RdClock		=> dspclk, 
		WrEn			=> wr_fifo, 
		RdEn			=> drdfifo, 
		Reset			=> reseth, 
		RPReset		=> reseth, 
		Q					=> data_out, 
		Empty			=> rdempty, 
		Full			=> wrfull,
		AlmostFull=> AlmostFull
	);

end Behaviour; --=================== End of architecture ====================--